Deadline-Based DMA Scheduling for Multi-Core Systems
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Solution Overview
Problem
In multi-core processor systems, existing DMA engine designs often fail to meet hard real-time deadlines due to chronological scheduling policies, which are sub-optimal in multi-threaded or multi-core environments, leading to potential delays and inefficiencies in memory access.
Innovation Solution
A DMA engine employing deadline-based scheduling in hardware, where priorities are assigned based on the severity of missing deadlines, allowing for preemption of transfers to ensure hard real-time deadlines are met, even under overload conditions, using a global free-running clock to implement deadlines and prioritize transfers based on urgency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If chronological scheduling policy is used in DMA engine, then device complexity is reduced and ease of operation is improved, but hard real-time deadlines cannot be guaranteed in multi-core systems
Solution Approach 1:
The patent implements dynamic scheduling where the DMA engine adapts its behavior based on deadline urgency. The scheduler continuously monitors transfer deadlines and dynamically adjusts scheduling decisions, allowing the system to guarantee hard real-time deadlines while maintaining operational simplicity through automated dynamic adaptation rather than static complex configurations
Solution Approach 2:
The patent introduces a deadline-based scheduler as an intermediary component between the DMA engine and memory subsystem. This scheduler acts as a mediator that receives transfer requests, prioritizes them based on deadline urgency, and coordinates their execution, thereby guaranteeing deadline compliance without requiring complex modifications to the underlying DMA hardware or memory interface
2Reliability
If deadline-based scheduling with preemption is implemented, then hard real-time deadlines are guaranteed, but device complexity and processing overhead increase
Solution Approach 1:
The patent implements dynamic scheduling where the DMA engine adapts its behavior based on deadline urgency. The scheduler continuously monitors transfer deadlines and dynamically adjusts scheduling decisions, allowing the system to guarantee hard real-time deadlines while maintaining operational simplicity through automated dynamic adaptation rather than static complex configurations
Solution Approach 2:
The patent introduces a deadline-based scheduler as an intermediary component between the DMA engine and memory subsystem. This scheduler acts as a mediator that receives transfer requests, prioritizes them based on deadline urgency, and coordinates their execution, thereby guaranteeing deadline compliance without requiring complex modifications to the underlying DMA hardware or memory interface
3Productivity
If chronological scheduling is used, then device complexity is minimized, but productivity and memory access efficiency deteriorate in multi-threaded environments
Solution Approach 1:
The patent implements dynamic scheduling where the DMA engine adapts its behavior based on deadline urgency. The scheduler continuously monitors transfer deadlines and dynamically adjusts scheduling decisions, allowing the system to guarantee hard real-time deadlines while maintaining operational simplicity through automated dynamic adaptation rather than static complex configurations
Solution Approach 2:
The patent introduces a deadline-based scheduler as an intermediary component between the DMA engine and memory subsystem. This scheduler acts as a mediator that receives transfer requests, prioritizes them based on deadline urgency, and coordinates their execution, thereby guaranteeing deadline compliance without requiring complex modifications to the underlying DMA hardware or memory interface
Data Source
AI summary
A direct memory access (DMA) engine schedules data transfer requests of a data processing system according to both an assigned transfer priority and the deadline for completing a transfer.