Deadlock Detection in Electronic Circuit Design Verification
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Solution Overview
Problem
Current methods for detecting deadlock conditions in electronic design verification either fail to differentiate between true and potential deadlocks or are limited by capacity, making them ineffective for larger designs.
Innovation Solution
A computer-implemented method using a linear temporal logic property and proof engine to perform deadlock checks, analyzing counterexamples for loop escape conditions, extracting relevant events, and adding waiver constraints to force a no-deadlock outcome, iteratively repeating the process until no counterexample is found or the loop escape is unreachable.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If current deadlock detection methods are used, then deadlock conditions can be detected, but they cannot differentiate between true deadlocks and potential deadlocks
Solution Approach 1:
The patent segments the deadlock detection process into distinct phases: initial deadlock detection, loop escape analysis, and waiver constraint application. By dividing the verification process into these segments, the system can identify and analyze specific conditions (loop escapes) that cause false deadlock detections, thereby improving differentiation between true and potential deadlocks
Solution Approach 2:
The patent introduces an intermediary analysis mechanism that examines counterexamples to determine whether they represent true deadlocks or potential deadlocks caused by loop escape conditions. This intermediary step acts as a mediator between the proof engine and the final verification result, enabling more accurate classification of deadlock types
2Productivity
If current deadlock detection methods are used, then small designs can be verified, but capacity limitations prevent verification of larger designs
Solution Approach 1:
The patent applies preliminary action by proactively identifying and addressing loop escape conditions before they cause verification failures. By analyzing counterexamples and extracting waiver constraints in advance, the system prepares the verification process to handle larger, more complex designs without being blocked by false deadlock detections
Solution Approach 2:
The patent adds another dimension to the verification process by introducing temporal analysis of counterexamples. Instead of simply detecting deadlocks, the system analyzes the sequence of events leading to deadlocks, examining whether loop escape conditions are reachable. This temporal dimension enables the system to handle larger designs by distinguishing between actual deadlocks and transient conditions
3Measurement precision
If iterative deadlock checking with loop escape analysis is performed, then true and potential deadlocks can be differentiated, but the process complexity increases
Solution Approach 1:
The patent applies partial action by selectively analyzing only those counterexamples that contain loop escape conditions. Rather than performing exhaustive analysis on all possible deadlocks, the system focuses computational resources on identifying and resolving loop escape scenarios, thereby improving deadlock classification without proportionally increasing overall process complexity
Data Source
AI summary
The present disclosure relates to a method for electronic circuit design. Embodiments may include receiving, using a processor, an electronic circuit design and performing a deadlock check on the electronic circuit design using a using a linear temporal logic property and a proof engine. Embodiments may further include analyzing a counterexample associated with the electronic circuit design for a loop escape condition, wherein analyzing includes proving a cover trace of a liveness obligation. If the loop escape condition is reachable from the counterexample, embodiments may include extracting one or more events associated with the loop escape condition and adding a waiver constraint to the deadlock check to force a no deadlock outcome.