Deadlock Detection in Electronic Design via Formal Verification

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Solution Overview

Problem

Current deadlock detection methods in electronic design verification are inefficient due to high computational intensity, reliance on user-provided stimuli, and the need for fairness constraints, which can lead to false negatives and are not scalable for complex designs, especially in multisystem SoCs.

Innovation Solution

A two-step formal verification technique that identifies deadlock candidates by sweeping the state space and determines if they are real deadlocks through a second search, eliminating the need for LTL liveness assertions and fairness constraints, and using formal verification to automatically calculate stimuli for deadlock detection.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional LTL liveness assertions are used for deadlock detection, then deadlock detection capability is provided, but computational intensity is high and scalability is poor

Engineering Contradiction:

Improvedeadlock detection capabilityVSAvoidcomputational efficiency

Core Design Contradiction:

ReliabilityVSProductivity

Solution Approach 1:

The patent segments the deadlock detection process into two distinct phases: (1) a first search phase that sweeps the state space to identify potential deadlock states, and (2) a second search phase that verifies whether the design can exit from those states. This segmentation divides the computationally intensive task into manageable portions, improving both efficiency and scalability while maintaining detection reliability.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent performs preliminary action by conducting the first search to identify deadlock candidates before performing the computationally heavier second search to verify them. This preliminary identification step filters out non-deadlock states early, reducing the overall computational burden and improving scalability to larger designs.

Inventive Principle:

Principle #10Preliminary action

2Reliability

If LTL liveness assertions with fairness constraints are used, then deadlock detection is attempted, but false negatives occur and user expertise is required

Engineering Contradiction:

Improvedeadlock detection accuracyVSAvoidease of use

Core Design Contradiction:

ReliabilityVSEase of operation

Solution Approach 1:

The patent implements self-service by automatically generating the verification search without requiring users to manually write LTL assertions or configure fairness constraints. The system autonomously performs the two-phase search process, eliminating the need for specialized formal verification knowledge and reducing false negatives caused by improper constraint configuration.

Inventive Principle:

Principle #25Self-service

3Ease of operation

If simulation techniques are used for deadlock detection, then user-provided stimulus can be tested, but effectiveness depends on user stimulus setup and timing requirements are hard to meet

Engineering Contradiction:

Improveuser control over test stimulusVSAvoiddeadlock detection effectiveness

Core Design Contradiction:

Ease of operationVSReliability

Solution Approach 1:

The patent substitutes the mechanical simulation approach with a formal verification system that performs exhaustive state space exploration. Instead of relying on user-crafted stimulus waveforms and timing arrangements, the system systematically searches through all possible states, guaranteeing detection effectiveness independent of user expertise or timing constraints.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

4Reliability

If CTL liveness assertions are used, then alternative deadlock checking is provided, but semantics are hard to explain and model checker support is limited

Engineering Contradiction:

Improvedeadlock verification capabilityVSAvoidformal verification complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent adopts a simpler, more accessible formal verification approach that does not require complex CTL semantics or extensive model checker support. By using a two-phase search method with straightforward state exploration, the system achieves reliable deadlock detection with lower complexity tools and easier-to-understand operation, making formal verification accessible to a broader user base.

Inventive Principle:

Principle #27Cheap short-living objects (Disposable)

Data Source

PatentUS10108767B1Methods, systems, and computer program product for implementing deadlock detection with formal verification techniques in an electronic design

Publication Date: 2018.10.23 CADENCE DESIGN SYST INC

AI summary

Disclosed are methods, systems, and articles of manufacture for implementing deadlock detection with formal verification techniques in an electronic design. These techniques identify one or more inputs that include at least an initial state of an electronic design and identify at least one deadlock candidate by sweeping at least a portion of a state space of the electronic design with formal verification techniques. These techniques then determine whether the at least one deadlock candidate is a real deadlock by using a second formal search with the formal verification techniques.