Deadtime Generator Circuit With Single-Feedback Non-Overlapping Clocks
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Solution Overview
Problem
Conventional deadtime generators require large logic components and consume significant power and area, limiting the achievable minimum delay and flexibility in generating non-overlapping clock signals.
Innovation Solution
A tunable deadtime generator circuit using a single feedback path with skewed inverters and transistors to generate non-overlapping clock signals, reducing the number of logic gates and power consumption while allowing adjustable deadtime values.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional deadtime generators use large logic components, then reliability is improved, but area consumption increases and power consumption increases
Solution Approach 1:
The patent combines multiple functions into a single feedback path that handles both clock signal inversion and deadtime generation. The feedback path integrates the inverter chain and the control logic for both output clocks, eliminating the need for separate logic components for each clock signal, thus reducing area while maintaining reliability
Solution Approach 2:
The feedback path serves multiple functions simultaneously: it generates inverted clock signals, controls the deadtime period, and regulates both first and second output clocks. This multi-functionality reduces the overall component count and area consumption while ensuring reliable operation through a unified control mechanism
2Reliability
If conventional deadtime generators use large logic components, then reliability is improved, but power consumption increases
Solution Approach 1:
The patent merges the control logic for multiple clock outputs into a single feedback path, reducing the total number of active logic components. Fewer logic gates mean lower static and dynamic power consumption while the feedback mechanism ensures reliable clock signal generation
Solution Approach 2:
The feedback path performs multiple functions including signal inversion, deadtime control, and output regulation for both clock signals. This multi-functional design reduces overall power consumption by eliminating redundant logic circuits while maintaining system reliability through integrated control
3Manufacturing precision
If conventional deadtime generators are designed for fixed deadtime, then manufacturing precision is improved, but adaptability decreases
Solution Approach 1:
The patent implements a tunable deadtime generator where the deadtime period can be dynamically adjusted by modifying the feedback path configuration. This allows the circuit to adapt to different operating conditions and frequency requirements while maintaining precise deadtime control through the feedback mechanism
4Reliability
If conventional deadtime generators use multiple feedback paths, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent consolidates multiple feedback paths into a single feedback path that controls both clock outputs. This unified approach reduces circuit complexity and the number of components while maintaining reliability through the feedback mechanism that ensures proper timing and synchronization of both outputs
Data Source
AI summary
A deadtime generator configured to output a pair of non-overlapping clock signals. A circuit is provide that includes an input node for receiving a clock signal; a first signal path coupled to the input node and having a first output node for outputting a first modified clock signal, wherein the first signal path includes a feedback node coupled to an input of a feedback inverter; a second signal path coupled to the input node and having a second output node for outputting a second modified clock signal, wherein second signal path includes a Low-to-High skewed inverter; and a feedback signal path coupled to second signal path and having a High-to-Low skewed inverter with an output coupled to a gate of at least one transistor, wherein an output of the at least one transistor is coupled to the feedback node.