Deblocking Filter Memory Management for HEVC

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Solution Overview

Problem

The existing image processing systems for HEVC require a large number of line memories due to the sequential processing of deblocking filters and sample adaptive offset filters, leading to frequent access to external memory, which is inefficient.

Innovation Solution

The proposed solution involves an image processing apparatus with a deblocking filter and a sample adaptive offset processing unit that stores and reads blocks from memory only when necessary, reducing external memory access by performing filter processes in a pipeline manner and using intermediate memories to store pixel data.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If filtering is performed for the entire vertical edge on a picture basis and then for the entire horizontal edge, then image quality is improved by removing block noise, but the number of line memories required increases greatly

Engineering Contradiction:
Improveimage qualityVSAvoidnumber of line memories
Core Design Contradiction:
Manufacturing precisionVSQuantity of substance

Solution Approach 1:

The patent divides the picture into multiple blocks and processes each block independently through pipeline stages. Instead of holding entire picture edges in memory, only current and previous blocks are maintained in pipeline buffers, reducing memory requirements while maintaining filtering quality

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent performs preliminary decoding and prepares block data in advance before filtering is needed. By pre-decoding blocks and maintaining them in pipeline buffers, the system avoids frequent external memory accesses during the filtering stage

Inventive Principle:
Principle #10Preliminary action

2Productivity

If a deblocking filter and sample adaptive offset filter are applied sequentially on an LCU basis, then coding efficiency is improved, but the number of external memory accesses increases

Engineering Contradiction:
Improvecoding efficiencyVSAvoidexternal memory access time
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The patent implements a continuous pipeline that processes multiple blocks simultaneously through overlapping stages of deblocking filtering and sample adaptive offset filtering. This eliminates idle time between operations and maintains continuous data flow, preventing external memory accesses

Inventive Principle:
Principle #20Continuity of useful action

Solution Approach 2:

The system pre-decodes and pre-processes blocks before they reach the filtering stages, so that when filtering occurs, all necessary data is already available in the pipeline buffers, eliminating the need for external memory accesses during filtering operations

Inventive Principle:
Principle #10Preliminary action

3Measurement precision

If filtering is performed on an LCU basis with line memories for each LCU edge, then local decoding accuracy is improved, but hardware complexity increases

Engineering Contradiction:
Improvelocal decoding accuracyVSAvoidhardware complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent segments the filtering process into discrete pipeline stages that handle individual blocks rather than requiring separate line memories for each LCU edge. This modular approach maintains processing accuracy while reducing hardware complexity

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The pipeline buffers serve multiple functions: they store decoded blocks, provide data for deblocking filtering, and supply input for sample adaptive offset filtering. This multi-functionality eliminates the need for separate dedicated line memories for each processing stage

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS9924163B2Image processing apparatus and image processing method
Publication Date: 2018.03.20 SONY GROUP CORP
  • US9924163B2 patent drawing
  • US9924163B2 patent drawing
  • US9924163B2 patent drawing

AI summary

An image processing apparatus includes a decoding unit, a deblocking filter, and a sample adaptive offset processing unit. The decoding unit is configured to perform a decoding process for a coded stream to generate an image. The deblocking filter is configured to store a block, a corresponding block of which on a current edge is not input, in a memory, out of blocks of the image generated by the decoding unit and read the block stored in the memory at timing when the corresponding block is input, to perform a filter process. The sample adaptive offset processing unit is configured to perform a sample adaptive offset process by using a pixel of the block that has been subjected to the filter process by the deblocking filter.