Debug Assert Mechanism for Multi-Core Error Tracking
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Solution Overview
Problem
Modern computing systems face challenges in efficiently collecting and processing debug information due to increasing data volumes, which hampers error detection and analysis, leading to performance issues and higher costs.
Innovation Solution
A computing system with a debug assert mechanism that uses volatile memory to detect errors, set flags, collect debug information, and generate assert dump information, which is then stored in non-volatile memory for further analysis, allowing tracking of error instances and improving robustness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If debug information is collected for all cores, then error detection capability is improved, but processing efficiency deteriorates due to increased data volume
Solution Approach 1:
The patent divides the debug information collection process by separating error-prone cores from normal cores. Error-prone cores have debug assert flags enabled to collect debug information, while normal cores continue processing without the overhead of debug collection. This segmentation allows selective debugging that maintains processing efficiency while improving error detection for problematic cores.
2Measurement precision
If debug information is collected for error-prone cores, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The patent implements a universal debug assert flag mechanism that can be applied to any core in the system. The same flag structure and collection process is used across all cores, providing a multi-functional solution that works for both error-prone and normal cores. This universal approach standardizes the debugging process and reduces overall system complexity despite enabling precise error tracking.
Data Source
AI summary
A computing system includes: a volatile memory configured to: store a debug assert flag mask including bits; cores, coupled to the volatile memory, configured to: detect an error in at least one of the cores, set at least one of the bits corresponding to the cores with the error detected, collect debug information for each of the cores with the error detected, collect operating information for each of the cores without the error detected, generate assert dump information based on compiling the debug information; and a nonvolatile memory, coupled to at least one of the cores, configured to: store the assert dump information, the operating information, configured to by at least one of the cores.