Debug Attention Register for Power Domain Management
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Debugging processes in data processing apparatuses are invasive due to the need for frequent transitions between powered and low power states, affecting the power profile and efficiency of debugging operations.
Innovation Solution
Implementing a debug attention register in a fully powered domain that indicates the status of debug event registers, allowing polling to occur only when the attention register is set, thereby reducing unnecessary power state transitions and minimizing the invasiveness of debugging activities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the debugger polls the debug event register frequently to detect debug events, then the reliability of debug event detection is improved, but the power consumption increases and the invasiveness of debugging activities worsens
Solution Approach 1:
The patent introduces an intermediary mechanism (debug attention register and power domain management) between the debugger and the debug event register. The debug attention register acts as a mediator that the debugger polls instead of directly polling the debug event register, allowing the power domain to remain in low power state when no debug events are pending, thus reducing power consumption while maintaining reliable debug event detection
Solution Approach 2:
The system performs preliminary action by setting the debug attention register in advance when a debug event occurs. This allows the debugger to detect pending events through the attention register before actually accessing the debug event register, enabling the system to wake up from low power state only when necessary, thereby reducing overall power consumption
2Use of energy by moving object
If the circuit block transitions to low power state to reduce power consumption, then the power efficiency is improved, but the ability to detect debug events timely deteriorates
Solution Approach 1:
The debug attention register serves as an intermediary that remains accessible even when the power domain is in low power state. This mediator allows the debugger to detect whether debug events are pending without requiring the power domain to be fully active, thus maintaining debug event detection capability while improving power efficiency
Solution Approach 2:
The system implements feedback through the debug attention register which is set by the circuit block when a debug event occurs. This feedback mechanism allows the debugger to know when to wake up the power domain, ensuring timely debug event detection while allowing the system to remain in low power state during normal operation
3Speed
If the debugger polls debug status registers frequently, then the speed of debug event detection is improved, but the invasiveness of debugging activities increases
Solution Approach 1:
The debug attention register acts as an intermediary that provides a lightweight polling target for the debugger. Polling this register is less invasive than polling the full debug status registers, as it requires fewer resources and has minimal impact on the circuit block operation, while still enabling fast detection of debug events
Data Source
AI summary
A data processing apparatus has at least one circuit block accessible for debugging by a debugger, the block having a set of debug status registers and a debug event register which is set by the circuit block to indicate occurrence of a debug event. Debug interface circuitry interfaces with the set of debug status registers for each circuit block. The circuitry includes at least a first portion which is in a first power domain that remains in a fully powered state while the debugger is connected to the circuitry. Status registers are provided in a second power domain which transitions between the fully powered state and at least one low power state while the debugger is connected to the circuitry. Content of the debug status registers is only accessible to the debugger when the second power domain is in the fully powered state.