Debug Barrier Transactions for IC Interconnect Ordering
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Solution Overview
Problem
Integrated circuits face limitations in debug operations due to a mismatch in communication speed between debug interfaces and the high-speed operations of the circuits, restricting the bandwidth for debug transactions and pin usage, which hinders effective debugging.
Innovation Solution
The integration of debug access port circuitry and interconnect circuitry within the integrated circuit that responds to debug commands to generate barrier transactions, constraining the relative ordering of data transactions and enhancing debug operations by buffering complex transactions, allowing for more sophisticated and accurate debugging without increasing the number of pins.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of connection pins is increased to support debug operations, then the bandwidth for debug transactions is improved, but the pin count increases which is undesirable
Solution Approach 1:
A barrier transaction mechanism is introduced as an intermediary to coordinate between debug transactions and data transactions. The barrier transaction acts as a mediator that constrains the relative ordering of transactions without requiring additional physical connection pins, thereby maintaining high debug operation rates while avoiding increased pin count.
2Speed
If the debug interface communication frequency is increased to match integrated circuit speed, then the bandwidth mismatch is resolved, but the complexity of the debug interface increases
Solution Approach 1:
The barrier transaction is generated in advance by the debug access port circuitry based on debug commands received from the external debug controller. This preliminary action allows the system to pre-establish transaction ordering constraints before the actual debug operations execute, enabling high-speed operation without requiring complex real-time coordination at the interface level.
3Adaptability or versatility
If complex debug circuitry is added to enable sophisticated debug operations, then the functionality is improved, but the device complexity increases
Solution Approach 1:
The debug functionality is segmented into distinct components: the external debug controller that sends commands, the debug access port circuitry that generates barrier transactions, and the interconnect circuitry that enforces transaction ordering. This segmentation allows sophisticated debug operations to be achieved without concentrating all complexity within a single debug circuitry block, distributing it across multiple functional units.
Data Source
AI summary
An integrated circuit 2 includes one or more transaction masters 8, 10, 12, 4 for issuing data transactions via interconnect circuitry 20. Debug access port circuitry is configured to respond to debug commands received from a debug controller 6 to generate barrier transactions which are issued to the interconnect circuitry. The interconnect circuitry responds to the received barrier transactions by constraining a relative ordering of at least some of the data transactions as they pass through the interconnect circuitry.