Debug Bus Steering Module for Power Gating Signal Observation
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Solution Overview
Problem
The existing Design for Debug (DFD) techniques face challenges in observing debug signals during power gating events, particularly when functional blocks upstream or downstream of powered-down blocks are affected, due to the daisy chain configuration and power gating techniques used in semiconductor chips.
Innovation Solution
A system that includes a debug path and a debug bus steering module, coupled with a logic analyzer/trace capture buffer and a power gating finite state machine, allowing debug signals from powered-down functional blocks to be passed along the debug path to an end functional block during power cycling, enabling observation across power gating cycles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If power gating techniques are used to save power during standby mode, then power consumption is reduced, but debug signal observation is blocked for functional blocks upstream of powered-down blocks
Solution Approach 1:
The debug path is segmented into multiple observable points, each equipped with its own buffer. This allows independent observation of debug signals at different locations in the daisy chain, enabling observation of upstream blocks even when downstream blocks are powered down. The segmentation creates multiple parallel observation channels that are not affected by power gating of individual functional blocks.
Solution Approach 2:
Buffers are introduced as intermediary components between functional blocks in the debug path. These buffers capture and store debug signals, acting as mediators that preserve signal information even when downstream functional blocks are powered down. The buffers decouple the observation function from the powered-down blocks, maintaining signal availability for debugging.
2Adaptability or versatility
If daisy chain configuration is used for debug wrappers, then debug coverage is extended across multiple functional blocks, but signal observation is prevented when upstream blocks are powered down
Solution Approach 1:
Buffers are pre-positioned at strategic locations in the daisy chain before powered-down blocks. These preliminary buffer placements ensure that debug signals are captured and stored in advance or at alternative observation points before power gating occurs, preserving signal availability for subsequent debugging operations even when upstream blocks are powered down.
Solution Approach 2:
The solution adds a temporal dimension to the daisy chain configuration by introducing buffers that operate independently of the power gating timeline. Buffers can capture signals during powered-up states and retain them for later observation, creating a time-separated observation mechanism that resolves the spatial constraint of the daisy chain during power gating events.
3Loss of energy
If functional blocks are powered down to reduce activity, then power saving is achieved, but debugging capability is lost for those blocks during power gating events
Solution Approach 1:
Buffers serve as intermediary storage elements that maintain debugging capability independent of functional block power state. These buffers capture debug signals when blocks are active and preserve them during power gating events, ensuring reliable observation and debugging capability is maintained even when functional blocks are powered down for power saving.
Solution Approach 2:
The buffer creates a copy or replica of the debug signal path that is independent of the functional block's power state. By buffering the signal, a persistent copy of the debug information is created that can be observed regardless of whether the original functional block is powered up or down, maintaining debugging reliability during power saving modes.
Data Source
AI summary
A system, method, and tangible computer readable medium for chip debug is disclosed. For example, the system can include a plurality of functional blocks, a debug path, and a debug bus steering module. The debug path couples the plurality of functional blocks in a daisy chain configuration, where an end functional block from the plurality of functional blocks is at an end of the daisy chain configuration. The debug bus steering module is configured to pass one or more debug signals associated with a first functional block from the plurality of functional blocks along the debug path to the end functional block while a second functional block from the plurality of functional blocks performs one or more power gating cycles.