Debug Chain for Test Clock Pulse Verification

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Solution Overview

Problem

Existing test circuits using ATPG or LBIST modes face issues in determining whether the generated test clock is operating correctly, leading to potential malfunctions and incorrect test results due to missed clock pulses.

Innovation Solution

A test circuit with a debug chain that operates in either clock debug or test mode, utilizing a linear feedback shift register and multiple input shift register, generates a clock debug signature to assess the test clock's correctness by storing and processing test pattern data with specific clocking mechanisms and scan enable signals.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If ATPG or LBIST techniques are used to test the device, then the test coverage and ability to detect faults is improved, but the reliability of test results deteriorates when missed clock pulses occur

Engineering Contradiction:

Improvetest result accuracyVSAvoidtest circuit complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The test circuit is divided into distinct functional modules: a debug chain for clock monitoring, a test data source for pattern generation, and a test data target for result comparison. This segmentation allows the clock monitoring function to be independently implemented and verified without complicating the overall test architecture.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

A debug chain is introduced as an intermediary component between the test data source and test data target. This intermediary specifically monitors clock pulses and generates debug signatures that indicate whether clock pulses were correctly received, thereby preventing incorrect test results without requiring complete redesign of the test circuit.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Difficulty of detecting and measuring

If the debug chain stores test pattern data and generates clock debug signatures, then the ability to detect missed clock pulses is improved, but the device complexity increases

Engineering Contradiction:

Improveclock pulse detection capabilityVSAvoiddebug chain complexity

Core Design Contradiction:

Difficulty of detecting and measuringVSDevice complexity

Solution Approach 1:

The debug chain is designed to perform multiple functions: storing test pattern data, generating clock debug signatures, and indicating clock pulse status. By making this component multi-functional, the patent avoids adding separate dedicated circuits for each function, thereby limiting the increase in device complexity while maintaining strong clock pulse detection capability.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS10302700B2Test circuit to debug missed test clock pulses

Publication Date: 2019.05.28 STMICROELECTRONICS INT NV

AI summary

Disclosed herein is a test circuit for a device under test. The test circuit includes a test data source and a test data target. A debug chain is coupled between the test data source and test data target, and operates in either a clock debug mode or a test mode. The debug chain, when in the test mode, is deactivated. The debug chain, when in the clock debug mode, receives the test pattern data from the test data source and stores the test pattern data, generates a clock debug signature from the stored test pattern data while clocked by a test clock, and outputs the clock debug signature to the test data target, the clock debug signature indicative of whether the test clock is operating properly.