Debug Circuit Detects External Debugger to Halt Processor at Reset
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Debugging systems, such as those with integrated processors, face challenges in gaining control of processors immediately after reset to halt their operation and program debug resources, making it difficult for external debuggers to effectively monitor and trace code execution.
Innovation Solution
A debug circuit that detects the presence of an external debugger upon system reset and halts processor operation, allowing the debugger to program trace sources and other debug resources without needing to gain direct control of the processors, and facilitates reprogramming upon power restoration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the processor starts running immediately after reset, then the system can begin operation quickly, but the debugger cannot program debug resources before the processor executes code
Solution Approach 1:
The debug circuit detects debugger presence before the processor begins execution and halts the processor in advance, providing the debugger with opportunity to program trace sources and debug resources before code execution starts. This preliminary halting action resolves the contradiction by ensuring debug resources are configured before the processor runs, while still allowing quick startup when no debugger is present.
2Ease of operation
If the debugger halts the processor to program debug resources, then the debugger can configure trace sources, but the system operation is delayed
Solution Approach 1:
The system performs the halting action preliminarily - only when a debugger is detected - so that debug resource programming can occur before processor execution. When no debugger is present, the processor starts immediately without halting, thus avoiding time loss. This conditional preliminary action resolves the contradiction by eliminating delays in normal operation while enabling proper debugging when needed.
3Productivity
If the processor runs immediately after reset, then system productivity is maintained, but trace continuity cannot be ensured during power losses
Solution Approach 1:
The debug circuit preliminarily halts the processor upon detecting a debugger, allowing configuration of trace sources to capture execution flow. This preliminary setup ensures that when power is restored after losses, the trace system is already configured and can immediately capture execution, ensuring trace continuity without sacrificing productivity during normal operation.
Data Source
AI summary
A system is disclosed comprising a processor, and a debug circuit. The debug circuit comprises a reset circuit configured to detect when the system is released from a reset, a debugger detection circuit configured to detect whether an external debugger is connected to the system at a time the reset circuit detects a release from the reset, and a halt circuit configured to halt operation of the processor when the debugger detection circuit detects the debugger at the time of release from the reset.