Debug Circuit Configures IO Pads to Indicate Reset Phase
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Solution Overview
Problem
Existing debug circuits for integrated circuits (ICs) are inadequate for debugging during the reset sequence, and incorporating dedicated debugging input/output (IO) pins increases area and cost, limiting their availability for functional purposes, especially when the IC is stuck in a reset phase and the processor cannot initiate debugging.
Innovation Solution
An integrated circuit (IC) with a debug circuit that includes logic gates, a pad control register, and a pad configuration register, which configures a general-purpose IO pad to logic high, logic low, or high impedance states to indicate the initialization status of circuits, allowing debugging without additional IO pins and without redesigning the IC.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If dedicated debugging IO pins are included in the IC, then debugging capability during reset sequence is improved, but area and cost increase, and functional IO pins are reduced
Solution Approach 1:
The patent applies multi-functionality by enabling general-purpose IO pads to serve dual purposes: both functional I/O operations and debugging operations. The debug circuit multiplexes the IO pad between functional mode and debug mode, allowing the same physical pin to perform different functions depending on the operating context. This eliminates the need for separate dedicated debugging pins while maintaining full debugging capability during reset sequence.
Solution Approach 2:
The patent introduces a debug circuit as an intermediary component that mediates between the existing IO pads and the debugging function. This intermediary multiplexer circuit enables the IO pad to be selectively connected to either functional signals or debug signals, allowing debugging without physical modification of the IC structure or addition of dedicated pins.
2Ease of operation
If dedicated debugging IO pins are included in the IC, then debugging capability during reset sequence is improved, but the number of functional IO pins is reduced
Solution Approach 1:
The patent implements universality by designing the IO pad to be configurable for multiple functions. Through the pad configuration register and control logic, the same physical IO pad can be dynamically assigned to either functional I/O operations or debugging operations, maximizing the utilization of available pins and maintaining full functional versatility without sacrificing debugging capability.
3Ease of operation
If the IC is stuck in a reset phase, then debugging becomes necessary, but the processor is unable to initiate debugging
Solution Approach 1:
The patent implements self-service by enabling the debug circuit to automatically activate and provide debugging functionality when the IC is stuck in a reset phase, without requiring processor intervention. The debug circuit monitors the reset sequence status and autonomously enables debugging modes, making the debugging process accessible even when the normal processor control path is blocked.
Solution Approach 2:
The patent employs feedback mechanisms where the debug circuit continuously monitors the reset sequence status and provides feedback signals to determine when debugging should be activated. This feedback loop enables the system to detect when the IC is hung in a reset phase and automatically make debugging accessible through the appropriate control logic and signal routing.
Data Source
AI summary
An integrated circuit (IC) operable in functional and debug modes includes a debug enable circuit, a pad control register, a debug circuit, a pad configuration register, and an input/output (IO) pad. The debug circuit receives a functional signal from a circuit monitoring circuit, a reference signal, a debug control signal from the debug enable circuit, and pull-enable control and pull-type select control signals from the pad control register, and generates pull-enable and pull-type select signals. The pad configuration register receives the pull-enable and pull-type select signals and configures the IO pad in one of logic low, logic high, and high impedance states. When the IO pad is in either of the logic high and low states longer than a predetermined time period, then the IO pad indicates that the IC is held in a reset phase of a reset sequence.