Debug Circuit Trace Register Annotation for Low-Bandwidth Tracing
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Solution Overview
Problem
Current debug trace modes in computer systems require recording information for all executed instructions, which increases bandwidth requirements and can disrupt program execution, making it difficult to insert debug messages without affecting the normal flow of the program, thereby reducing the accuracy of trace results.
Innovation Solution
A novel digital circuit that uses a trace register to annotate a trace stream with data values and core register information, allowing for the insertion of debug messages with minimal disruption, and a low-bandwidth trace mode that limits trace data to subroutine call and return instructions to reduce execution impact.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of information
If debug trace mode records information for all executed instructions, then trace data completeness is improved, but bandwidth requirements increase and program execution is disrupted
Solution Approach 1:
The patent segments the trace data into two categories: essential trace information (program counter, branch information) that is always collected, and optional debug information (register values, memory contents) that is collected selectively based on breakpoints and triggers. This segmentation reduces the overall bandwidth requirements while maintaining trace data completeness for essential debugging functions.
Solution Approach 2:
The patent applies local quality by collecting detailed debug information only at specific locations in the program execution (breakpoints, triggers, exception handlers) rather than uniformly across all instructions. This allows the system to maintain high trace data quality where needed while reducing bandwidth consumption in other regions.
2Adaptability or versatility
If debug messages are inserted into trace stream, then debugging capability is improved, but program execution disruption increases
Solution Approach 1:
The patent prepares debug information in advance by pre-configuring breakpoints, triggers, and filter criteria before program execution. This preliminary action allows the debug circuit to efficiently capture and insert relevant debug messages without requiring real-time processing that would disrupt program execution.
Solution Approach 2:
The patent introduces a debug circuit as an intermediary component that sits between the program execution and the trace stream. This intermediary selectively captures debug information and inserts it into the trace stream without directly interfering with the normal program execution flow, thereby maintaining both debugging capability and execution speed.
3Productivity
If low-bandwidth trace mode limits trace data to subroutine calls and returns, then execution impact is reduced, but trace data detail is lost
Solution Approach 1:
The patent implements dynamic trace data collection by allowing the trace mode to switch between different levels of detail based on execution context. In normal execution, only essential trace information is collected to maintain high execution speed. When breakpoints or triggers are encountered, the system dynamically increases the detail level to capture comprehensive debug information.
Solution Approach 2:
The patent changes the parameter of trace data granularity based on execution conditions. By adjusting the amount and type of trace information collected according to specific events (breakpoints, exceptions, function calls), the system optimizes the balance between execution speed and trace data detail, ensuring sufficient information is available for bug diagnosis without excessive bandwidth consumption.
Data Source
AI summary
An apparatus includes a processor circuit that includes a memory circuit, one or more processor cores, and a debug circuit. The debug circuit may be configured, in response to activation of a trace mode to record information indicative of instructions executing on the one or more processor cores, to write a trace data stream to the memory circuit that includes trace data collected on the instructions executing on the one or more processor cores. In response to a particular instruction within one of the processor cores specifying a write of a data value to an architecturally visible trace register, the debug circuit may be further configured to output the data value to the trace data stream as part of executing the particular instruction.