Multi-Core Processor Debug Circuitry for Low-Power Signal Transmission

The debug circuitry is segmented into multiple independent debug circuits, each associated with a specific core. Each debug circuit includes event generating, clearing, and responding circuitries that operate independently, allowing selective activation and reducing overall power consumption while maintaining full debug functionality across multiple cores.

The patent implements dynamic control of debug event signal transmission through transmission controllers that can selectively enable or disable signal paths based on operational needs. The master control circuit dynamically manages the timing and routing of debug events, allowing the system to transition between active debugging and low-power states, thereby reducing average power consumption.

The debug circuits are designed with self-configuring capabilities where the event generating circuitry automatically sets up the necessary signal transmission paths when a debug event occurs. The transmission controllers and master control circuit work together to automatically route debug events to the appropriate targets without requiring manual register configuration, thereby reducing system complexity while maintaining synchronous transmission capability.

The master control circuit serves multiple functions: it generates debug events, controls transmission timing, routes signals to appropriate debug circuits, and manages the overall synchronization. This multi-functional design eliminates the need for separate dedicated control registers for each function, reducing the overall number of configuration registers required while achieving reliable synchronous debug event signal transmission across all cores.