External Debug Clock Delay Compensation for High-Speed Data Input
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Solution Overview
Problem
Current automotive test interfaces face challenges in achieving high data throughput due to timing constraints and delays in data communication between external test tools and vehicle computers, limiting the frequency of the test clock and thus the data transfer rate.
Innovation Solution
A testing tool with a programmable delay circuit that generates a delayed version of the test clock to compensate for transmission delays, allowing the data input circuitry to be clocked at the correct time, thereby increasing the test clock frequency and data throughput.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the test clock frequency is increased to achieve higher data throughput, then data transfer rate is improved, but timing constraints are violated due to unchanging transmission delays
Solution Approach 1:
The patent applies preliminary action by measuring the transmission delay between the test clock output and data input circuitry beforehand, then pre-calculating and applying a compensating delay to the test clock signal. This allows the system to operate at higher clock frequencies while maintaining proper timing alignment, as the delay compensation is established in advance rather than reactively adjusting during operation.
Solution Approach 2:
The patent changes the parameter of test clock frequency to achieve higher data throughput, while simultaneously adjusting the delay parameter of the test clock signal through the programmable delay circuit. By dynamically adjusting the delay parameter in response to clock frequency changes, the system maintains timing constraint compliance even as the operating frequency increases.
2Productivity
If the test clock frequency is increased to improve data transfer rate, then productivity is improved, but transmission delays become significant relative to clock period
Solution Approach 1:
The system performs preliminary measurement of the transmission delay through the connector and circuitry, then pre-applies compensating delay to the test clock signal. This allows the clock frequency to be increased without the transmission delay becoming a significant portion of the clock period, as the compensation is already in place to offset the fixed transmission time.
Solution Approach 2:
The programmable delay circuit acts as an intermediary between the test clock source and the data input circuitry. It introduces a controllable delay that compensates for the fixed transmission delays in the physical connector and circuitry, thereby reducing the effective relative transmission delay and enabling higher clock frequencies.
3Productivity
If standard debugging interface is used, then device complexity is low, but data throughput is limited by timing constraints
Solution Approach 1:
The patent introduces a programmable delay circuit as an intermediary component in the debugging interface. This additional component enables higher data throughput by compensating for transmission delays, accepting the necessary increase in device complexity as a trade-off for achieving the required performance level.
Solution Approach 2:
The system performs preliminary characterization of the transmission path to determine the exact delay values, then configures the programmable delay circuit accordingly. This preliminary setup enables the interface to operate at higher speeds while maintaining timing accuracy, justifying the added complexity through significant performance improvement.
Data Source
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AI summary
A testing tool (10) includes a clock generation circuit (16, 18, 22) generating a test clock (Tck) and outputting the test clock via a test clock output pad (31), data processing circuitry (19) clocked by the test clock, and data output circuitry (20) receiving data output from the data processing circuitry and outputting the data via an input/output, IO pad (32), the data output circuitry being clocked by the test clock. The testing tool also includes a programmable delay circuit (41) generating a delayed version of the test clock (DELAYED_TCK), and data input circuitry (21) receiving data input via the IO pad, the data input circuitry clocked by the delayed version of the test clock (DELAYED_TCK). The delayed version of the test clock is delayed to compensate for delay between transmission of a pulse of the test clock via the test clock output pad to an external computer (50) and receipt of the data input from the external computer via the IO pad.