Debug Control Circuit Split Transaction Bus Arbitration
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Solution Overview
Problem
In debugging systems for semiconductor devices, there is a challenge in efficiently managing bus access rights between the CPU and the debugging circuit, leading to collisions and reduced efficiency in parallel program execution and parameter tuning.
Innovation Solution
The integration of a debugging circuit connected to an internal bus with a direct memory access controller (DMAC), allowing external debugger software to control the DMAC for direct data access to internal resources without CPU intervention, and implementing a split transaction mechanism to free bus usage rights, thereby avoiding collisions and optimizing bus usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the debugging circuit directly accesses internal resources via the bus in parallel with CPU execution, then debugging efficiency and parameter tuning capability are improved, but bus right acquiring requests collide between the debugging circuit and CPU
Solution Approach 1:
The system performs preliminary actions by having the CPU issue a command transfer request to the debugging circuit before the actual command transfer occurs. This preliminary request allows the debugging circuit to prepare for bus access and the system to establish proper bus arbitration timing, preventing collisions between CPU and debugging circuit access requests.
Solution Approach 2:
The bus right management is made dynamic through the split transaction mechanism. The bus right is temporarily transferred from the CPU to the debugging circuit during command transfer operations, and the timing of this transfer is dynamically controlled based on the command transfer request. This dynamic right transfer prevents static conflict while enabling efficient parallel debugging operations.
2Ease of operation
If the CPU halts execution to request command transfer to the debugging circuit, then debugging control is improved, but bus usage efficiency is reduced due to idle periods
Solution Approach 1:
The CPU issues the command transfer request in advance before actually needing the command data. This preliminary request allows the debugging circuit to prepare the command for transfer, so that when the CPU resumes bus access, the command is already ready, eliminating idle waiting time and maintaining high bus utilization while preserving debugging control capability.
Data Source
AI summary
A method and apparatus store a command in a command register and set, with a control circuit, a first operation mode associated with a split transaction for freeing a bus in a time period between a command transfer request and a command transfer operation. The method and apparatus set, with the control circuit, a second operation mode in which a split transaction is not issued and transfer, with the control circuit, the command to a processing unit via the bus in response to the command transfer request when in the second operation mode where after the processing unit executes the command and issues a subsequent command transfer request to the control circuit, the control circuit performs the split transaction when in the first and second operation modes.