Debug Controller Circuit for SoC Latency Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current debugging processes for complex System-on-Chip (SoC) devices are hindered by high latency and slow data transfer rates due to sequential execution of debug steps and the limitations of the JTAG interface, which prolongs the time required for testing and debugging.
Innovation Solution
A circuit arrangement and method that includes input and response buffers on the SoC, coupled with a transaction control circuit to process debug packets by decoding operation codes and determining the appropriate interface circuits for accessing storage circuits, enabling high-speed data transfer and concurrent debugging of multiple SoCs through a unified interface.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If sequential debug step execution through JTAG interface is used, then debugging can be performed with standard interface, but debugging time is excessively long due to high latency and slow clock rate
Solution Approach 1:
The debug packet is segmented into multiple operations that can be executed concurrently. The transaction control circuit divides the debug packet into operation codes, each targeting different interface circuits and storage circuits within the SoC, allowing parallel execution rather than sequential processing.
Solution Approach 2:
Multiple operations are prepared and staged within the debug packet before execution begins. The transaction control circuit pre-decodes operation codes and prepares access requests for multiple interface circuits simultaneously, eliminating the need to wait for each operation to complete before starting the next one.
2Adaptability or versatility
If JTAG interface circuitry operates at standard clock rate, then interface compatibility is maintained, but data transfer rate is limited to less than 100 MHz
Solution Approach 1:
The transaction control circuit acts as an intermediary between the JTAG interface and the internal SoC resources. It receives debug packets through the standard JTAG interface at compatible speeds, then internally processes and executes multiple operations in parallel at higher speeds, effectively bridging the speed gap between external interface and internal processing capabilities.
3Device complexity
If one debug packet accesses one storage circuit through one interface circuit, then access control is simple, but concurrent access to multiple SoC subsystems is not possible
Solution Approach 1:
The debug packet is segmented into multiple operation codes, each specifying a different interface circuit and storage circuit to access. This segmentation enables the transaction control circuit to distribute operations across multiple interface circuits simultaneously, achieving concurrent access to multiple SoC subsystems while maintaining relatively simple control logic.
Solution Approach 2:
The transaction control circuit is designed with universal functionality to handle multiple types of operations simultaneously. It can decode different operation codes and route them to appropriate interface circuits and storage circuits, making a single debug packet capable of accessing multiple different subsystems through multiple interface circuits in parallel.
Data Source
Figure 1
Figure 2
Figure 3
AI summary
A circuit arrangement includes one or more input buffers (312, 314,..., 316) disposed on a system-on-chip (SoC) (102) and configured to receive and store streaming debug packets. One or more response buffers (328, 330,..., 332) are also disposed on the SoC. A transaction control circuit (318) is disposed on the SoC and is configured to process each debug packet in the one or more input buffers. The processing includes decoding an operation code in the debug packet, and determining from an address in the debug packet, an interface circuit of multiple interface circuits to access a storage circuit in a subsystem of multiple sub-systems on the SoC. The processing further includes issuing a request via the interface circuit to access the storage circuit according to the operation code, and storing responses and data received from the interface circuits in the one or more response buffers.