Debug Controller Two-Stage Read Protocol for SoC Latency
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Solution Overview
Problem
Integrated circuits, such as SoCs, often require debugging even after production, but conventional debugging methods using SPI protocols struggle with latency issues when accessing internal resources, leading to failures in delivering responses within the limited timeframe.
Innovation Solution
A debug controller implementing a two-stage read command protocol, where a read-fetch command accesses data and stores it in a reservation register, and a read-publish command publishes the data to the host debugger, along with status indicators for latency tolerance, and utilizes the AXI bus protocol for priority access.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional SPI protocol is used for debugging, then device compatibility is maintained, but latency issues occur when accessing distant internal resources
Solution Approach 1:
The patent segments the debugging interface into two distinct components: a legacy SPI interface for maintaining compatibility and an AXI interface for high-speed access. The debug controller translates between these interfaces, allowing distant resources to be accessed via AXI (reducing latency) while preserving SPI compatibility for existing devices.
Solution Approach 2:
The debug controller acts as an intermediary between the SPI debugger and the SoC's internal resources. It receives commands from the SPI interface, translates them into AXI transactions for efficient access to distant resources, and returns results, thereby resolving the latency issue while maintaining SPI compatibility.
2Ease of operation
If external access port is added for debugging, then debugging capability is enabled, but device complexity increases
Solution Approach 1:
The debug controller is designed to handle multiple protocols (SPI and AXI) and perform multiple functions (protocol translation, command routing, data buffering). This multi-functionality allows a single component to enable debugging capability while managing the complexity through consolidation rather than adding multiple separate components.
Solution Approach 2:
The debug controller autonomously manages the translation between SPI and AXI protocols, handles command parsing, and performs data buffering without requiring additional external control logic. This self-service capability reduces the overall system complexity by embedding the necessary functionality within the controller itself.
3Speed
If priority access is implemented for debug controller, then debugging speed is improved, but resource allocation complexity increases
Solution Approach 1:
The AXI interconnect is configured with pre-established priority rules that automatically grant the debug controller priority access to distant resources. This preliminary configuration of priority levels eliminates the need for dynamic resource allocation decisions during debugging operations, maintaining high speed while avoiding complex runtime management.
Data Source
AI summary
A system includes a host debugger to carry out a debugging flow on a computing device and a debug controller to couple the host debugger to the computing device. The debug controller receives a bit stream from the host debugger, converts the incoming bit stream into a command according to a protocol, determines whether the command is a first-stage read command or a second-stage read command, and issues the first-stage read command to a data path of the computing device. If the command is a second-stage read command, the debug controller causes a reservation register of the debug controller to provide a data value or status indication to the host debugger through the interface. The reservation register contains read data returned by the first-stage read command and, in response to the second-stage read command, provides a status indication when the first-stage read command has not yet returned read data.