On-Chip Debug Emulator Parallel Serial Clock Synchronization
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Solution Overview
Problem
Current on-chip debug emulators (OCD) are expensive due to the use of high-priced Field Programmable Gate Arrays (FPGA) for JTAG controller functions, and there is a need to reduce costs further while maintaining debugging efficiency, especially since general-purpose microcomputers lacking internal parallel I/F circuits are not available at low costs.
Innovation Solution
Implementing an on-chip debug emulator with a debug communication control unit containing multiple serial communication circuits that operate synchronized with a clock signal, allowing parallel data transmission without the need for parallel communication circuits, thereby utilizing a low-cost microcomputer and eliminating the need for expensive FPGA devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If expensive FPGA devices are used for JTAG controller functions in OCD, then debugging control capability is improved, but device cost increases significantly
Solution Approach 1:
The patent replaces expensive FPGA devices with a general-purpose microcomputer that has sufficient processing power for JTAG controller functions but lacks internal parallel I/F circuits. This substitution dramatically reduces device cost while maintaining debugging control capability, as the microcomputer can perform the required control functions without needing expensive dedicated hardware
Solution Approach 2:
The patent introduces a parallel communication interface circuit as an intermediary component that bridges the gap between the general-purpose microcomputer and the target device. This intermediary enables parallel communication capability without requiring the microcomputer to have built-in parallel I/F circuits, thus maintaining low cost while achieving the required functionality
2Ease of manufacture
If general-purpose microcomputers without internal parallel I/F circuits are used, then device cost is reduced, but parallel communication capability is lost
Solution Approach 1:
The patent introduces a parallel communication interface circuit as an intermediary component that bridges the gap between the general-purpose microcomputer and the target device. This intermediary enables parallel communication capability without requiring the microcomputer to have built-in parallel I/F circuits, thus maintaining low cost while achieving the required functionality
Solution Approach 2:
The patent separates the parallel communication function from the microcomputer by implementing it as a distinct external interface circuit. This segmentation allows the microcomputer to remain a simple, low-cost general-purpose device while the specialized parallel communication tasks are handled by the dedicated interface circuit
Data Source
AI summary
An on-chip debug emulator is capable of connecting to the target device and the host device for remotely debugging the program in the target device. The on-chip debug emulator contains a debug communication control unit. This debug communication control unit contains a plurality of serial communication circuits, the plurality of serial communication circuits are commonly provided with a clock signal. The debug communication control unit controls communications with the target device based on commands output from the host device. Each of The plurality of serial communication circuits contains a data buffer and serially transmits data stored in the data buffer to and from the target device while synchronized with the clock signal. Namely, the plurality of serial communication circuits communicate in parallel while operating synchronized with the same clock. The on-chip debug emulator can in this way be made utilizing a low-cost microcomputer not containing any parallel communication circuits.