Hardware Integrated Debug Framework for Embedded Core Dump Retrieval
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Solution Overview
Problem
During the debugging of mobile devices, severe system malfunctions can lead to data loss and inaccessible core dumps, especially when the system fails to generate a core dump due to kernel panics or hardware failures, making it difficult to diagnose and recover from such events.
Innovation Solution
A hardware integrated debug framework that allows access to both volatile and nonvolatile memory of a debug target device, enabling a debug host device to acquire and create a core dump, even in failed states, by accessing processor registers and specific memory locations through a networked connection, and using specialized hardware to simulate or replace non-functional components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of information
If the system uses traditional volatile memory core dump generation, then debugging information can be captured, but the data is lost when the system loses power or resets
Solution Approach 1:
The patent creates a copy of the core dump data in non-volatile memory (NVM) alongside the traditional volatile memory (DRAM) storage. This copying mechanism ensures that debugging information is preserved even when the system loses power or resets, as the NVM copy remains intact while the volatile memory copy can be lost.
2Loss of information
If the system generates a complete core dump of volatile memory, then comprehensive debugging information is obtained, but data remains inaccessible if the system cannot successfully restart
Solution Approach 1:
The patent introduces a debug host device as an intermediary that accesses the target device's NVM through a debug interface. This intermediary enables retrieval of core dump data from NVM even when the target device cannot restart or boot properly, as the debug host can directly read the preserved data without requiring the target system to be operational.
3Loss of energy
If the system stores core dump data only in volatile memory, then fast write operations are achieved, but the data is lost on system reset
Solution Approach 1:
The patent merges the functionality of volatile memory (for fast writing during operation) and non-volatile memory (for data persistence) into a unified core dump storage system. The NVM is configured to mirror the DRAM structure, allowing the same core dump generation logic to write to both memory types simultaneously, thus achieving both speed and persistence without requiring separate storage systems.
4Ease of operation
If the debug interface accesses only volatile memory, then simple access operations are performed, but data cannot be retrieved after system failure
Solution Approach 1:
The patent extends the debug interface's functionality to access both volatile memory (DRAM) and non-volatile memory (NVM) through the same interface. This multi-functionality allows the debug interface to retrieve core dump data from either memory type depending on the system state, ensuring data accessibility whether the system is running, reset, or in a failed state.
Data Source
AI summary
Methods, machine-readable tangible storage media, and data processing systems that enable a debug host device to acquire memory dump information from a debug target device after the target device suffers an unrecoverable system malfunction are disclosed. In one embodiment, data in the volatile memory on a debug target device is accessed via a hardware integrated debug framework, which is also used to access data on a nonvolatile electronically erasable semiconductor memory of a debug target device, and one or more registers of one or more processors on a debug target device, and a core dump is created on the debug host device.