Debug Interconnect Bandwidth Management for SoC Power Domains
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Solution Overview
Problem
Modern system on chips (SoCs) and integrated circuits face challenges in debugging due to multiple low power domains and insufficient debug bandwidth, which leads to bottlenecks and difficulties in debugging firmware and low power operations, especially when debug data collides with functional traffic.
Innovation Solution
A power-aware dynamic bandwidth debug architecture that dynamically controls debug bandwidth and power consumption, using a bandwidth management architecture (BMA) with dynamic voltage and frequency scaling (DVFS) and dynamic bandwidth management (DBMS) to manage concurrent transactions and optimize resource usage, enabling effective debugging across various power states and operational modes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If debug data is sent in-band with functional traffic, then bandwidth utilization is improved, but debug performance deteriorates due to bottlenecks and collisions
Solution Approach 1:
The patent segments the communication bandwidth into separate channels: a first channel dedicated to functional traffic and a second channel dedicated to debug traffic. This segmentation prevents debug data from colliding with functional traffic, eliminating bottlenecks while maintaining high bandwidth utilization through coordinated resource allocation by the interconnect fabric.
2Use of energy by moving object
If power consumption is reduced for longer battery life, then energy efficiency is improved, but debug capability deteriorates due to multiple low power domains
Solution Approach 1:
The interconnect fabric serves multiple functions: it handles both functional traffic and debug traffic, and dynamically allocates bandwidth between them based on operational mode. The fabric can operate in different configurations (first mode for functional traffic, second mode for debug traffic) allowing the system to maintain debug capability across multiple power states while optimizing power consumption for each state.
Solution Approach 2:
The system dynamically switches between operational modes: in normal operation, the interconnect fabric prioritizes functional traffic; when debug is needed, it dynamically reconfigures to prioritize debug traffic. This dynamic adaptation allows the system to maintain low power consumption during normal operation while providing full debug capability when required, regardless of the power state of individual domains.
3Reliability
If debug bandwidth is allocated to ensure reliable debug data transfer, then debug reliability is improved, but functional performance deteriorates due to bandwidth contention
Solution Approach 1:
The interconnect fabric acts as an intermediary that mediates between functional traffic and debug traffic requirements. It implements intelligent bandwidth allocation, routing debug traffic through dedicated paths when needed while preserving functional performance. The fabric can dynamically adjust bandwidth allocation based on operational mode, ensuring reliable debug data transfer without permanently sacrificing functional performance.
Data Source
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AI summary
In one embodiment, a bandwidth management controller is coupled to a debug interconnect to dynamically allocate buffer space of a plurality of data buffers to hardware trace information, software trace information, and firmware trace information. The bandwidth management controller further includes a control logic to dynamically control at least one of a voltage and a frequency of the debug interconnect based at least in part on a debug activity level or a functional activity level. Other embodiments are described and claimed.