On-Chip Debug Logic for Monitoring Code Integrity
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Solution Overview
Problem
Conventional methods for monitoring the confidentiality and integrity of a target system, especially in embedded systems, face challenges due to the requirement for special hardware and inability to detect cache attacks, as well as inefficiencies in software-based approaches that can be bypassed by malware with similar privileges.
Innovation Solution
An apparatus that uses on-chip debug logic to monitor and control data load and store instructions, generating debug events to detect and prevent malicious activities, thereby ensuring the confidentiality and integrity of code and data areas, and can be installed either inside or outside the target system.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If hardware-based monitoring is used to detect code area writes, then monitoring reliability is improved, but device complexity increases due to special hardware requirements
Solution Approach 1:
The patent replaces complex external hardware monitoring systems with the processor's built-in debug logic, substituting a mechanical/physical monitoring apparatus with an integrated software-controlled mechanism that uses existing processor resources to achieve the same security monitoring function
Solution Approach 2:
The patent makes the processor's debug logic serve dual purposes: its original debugging function and the new security monitoring function for detecting code integrity violations, thereby eliminating the need for dedicated special-purpose hardware
2Measurement precision
If PCI card-based memory monitoring is used to detect tampering, then monitoring precision is improved, but ease of operation deteriorates due to special hardware installation requirements
Solution Approach 1:
The system uses the target processor's own built-in debug logic to perform self-monitoring of code integrity, eliminating the need for external PCI cards or additional hardware devices that would complicate installation and operation
3Difficulty of detecting and measuring
If bus-snooping method is used to monitor memory attacks, then detection capability is improved, but adaptability deteriorates because cache attacks cannot be detected
Solution Approach 1:
The patent segments the monitoring approach by instruction type, creating separate detection mechanisms for instruction fetches, data loads, and data stores, allowing each segment to be optimized for detecting specific attack vectors including cache-based attacks that bypass traditional bus monitoring
4Ease of manufacture
If software-based monitoring using page tables is used, then ease of manufacture is improved, but reliability deteriorates because malware with same privilege can bypass detection
Solution Approach 1:
The patent introduces an intermediary mechanism using the processor's debug logic that operates at a higher privilege level than standard software, creating a intermediate layer between the hardware and the OS that can detect violations without being bypassed by malware running at normal privilege levels
Data Source
AI summary
An apparatus and method for monitoring the confidentiality and integrity of a target system. The apparatus for monitoring the confidentiality and integrity of a target system includes a target area information reception unit for receiving target area information about a target area of the target system and storing the target area information, a monitoring unit for extracting attack information by monitoring at least one of confidentiality, corresponding to a data load instruction, and integrity, corresponding to a data store instruction, based on the target area information, and an attack-handling unit for determining whether an attack is occurring based on the extracted attack information and for handling the attack when it is determined that an attack is occurring.