Debug Memory Interface for Pin-Constrained Chips
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Solution Overview
Problem
Conventional chip debugging requires dedicated debug tools and pins, which are not suitable for small chips with simple circuit structures, and raises safety concerns due to the need for simulating a processor and accessing all chip components.
Innovation Solution
A chip with a debug memory interface that includes a processing unit, internal storage, detection unit, and memory interface management, allowing for debugging without additional pins by detecting an external memory device and triggering a debug program execution based on status data, using a serial peripheral interface and multiplexer to manage pin connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If dedicated debug tools and pins are used for chip debugging, then debugging capability is achieved, but pin quantity and circuit complexity increase
Solution Approach 1:
The existing memory interface pins are designed to serve dual purposes: normal memory access during chip operation and debug mode activation when specific voltage levels are detected. The detection unit monitors voltage levels on these existing pins to determine whether to switch to debug mode, eliminating the need for separate dedicated debug pins and reducing overall pin quantity while maintaining full debugging capability
Solution Approach 2:
The patent combines the memory interface circuit with the debug interface circuit into a single unified structure. The same physical pins and underlying circuitry are used for both normal memory operations and debug operations, with the detection unit and processing unit coordinating to switch between these two functional modes based on voltage level detection, thereby reducing circuit complexity while preserving both functionalities
2Ease of operation
If dedicated debug pins are added to enable debugging, then debugging function is achieved, but the chip structure becomes more complex
Solution Approach 1:
The memory interface pins are designed to perform multiple functions: serving as normal data/address lines during standard operation and as debug mode trigger lines when specific voltage patterns are detected. This multi-functional design allows the chip to achieve full debugging capability using the same physical infrastructure already present for memory operations, thereby adding no extra pins or structural complexity while enabling comprehensive debug functionality
3Ease of operation
If debug tool simulates processor with full access permission, then debugging capability is improved, but chip safety is compromised
Solution Approach 1:
The patent extracts and isolates the detection function into a separate detection unit that operates independently from the processing unit. This detection unit monitors voltage levels and triggers debug mode only when specific conditions are met, rather than allowing the processing unit to have unrestricted access to all chip components. This separation limits the scope of access during debugging while maintaining effective debug capability
Solution Approach 2:
The detection unit serves as an intermediary between the external debug environment and the internal chip components. It monitors voltage levels on the memory interface pins and conditionally triggers debug mode based on detected patterns, acting as a gatekeeper that controls when and how debug access is granted. This intermediary mechanism enables debugging functionality while maintaining chip safety by preventing unauthorized or unrestricted access to sensitive internal components
Data Source
AI summary
A chip having a debug memory interface includes a processing unit, an internal storage unit, a debug memory interface, and a detection unit. The internal storage unit is used to record status data during operation of the processing unit. The detection unit is used to detect whether the debug memory interface is electrically connected to an external memory device. When the debug memory interface is judged to be electrically connected to the external memory device, a control signal is transmitted to the processing unit in order to trigger the processing unit to read a debug program from the external memory device and execute the debug program to run a debug mode based on the status data.