Debug Data Memory Programming Upon System Failure
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In embedded electronic systems, the repetitive writing of diagnostic information to memory devices for debug purposes leads to unnecessary wear and resource consumption, affecting system performance during normal operation.
Innovation Solution
A system and method that utilize a timer, buffer, and register to program debug data to a memory device only upon system failure, reducing repetitive writes and resource usage by storing data at a designated address space when the timer reaches zero, allowing the system to remain operational and minimize wear on memory devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If diagnostic information is written to memory device repeatedly at periodic intervals, then debug information is available for system failure analysis, but memory device wear increases and system resources are consumed during normal operation
Solution Approach 1:
The system prepares debug data in advance by collecting it in a buffer during normal operation, and only writes it to the memory device when a timeout condition indicates system failure. This preliminary collection without immediate writing reduces memory wear while ensuring debug information is ready when needed.
Solution Approach 2:
The patent extracts the diagnostic write operation from periodic execution and conditions it only on timeout/failure events. By separating the data collection function from the write operation, the system maintains debug capability while eliminating unnecessary writes that cause memory wear during normal operation.
2Reliability
If diagnostic information is written to memory device repeatedly, then debug information is available, but system resources (memory data bus and address/control bus) are consumed affecting normal system performance
Solution Approach 1:
The system performs preliminary data collection in a buffer without triggering resource-intensive write operations during normal operation. Only when timeout occurs does the system execute the write operation, thus preserving system resources during normal performance-critical periods while still preparing debug information in advance.
Solution Approach 2:
The patent transforms continuous periodic writes into event-triggered writes based on timeout conditions. This changes the action frequency from regular periodic intervals to rare failure-event intervals, dramatically reducing resource consumption on the memory data bus and address/control bus during normal system operation.
Data Source
AI summary
A system and method for programming a memory device with debug data upon a system failure is disclosed herein. For example, the system can include a timer device, a buffer, a register, and a memory device. The buffer can be configured to receive debug data. The register can be configured to receive memory address information. Also, the memory device can be configured to store the debug data from the buffer at a memory address corresponding to the memory address information when a timer value of the timer device reaches zero. Further, the system can include a processing unit configured to provide the timer value to the timer device and the memory address information to the register.