Processor Debug Pipeline with On-Demand Power Isolation

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Solution Overview

Problem

Conventional processor on-chip debugging circuitry consumes energy continuously, reducing power efficiency due to integrated debug circuitry in the execution pipeline, even when not being used for debugging.

Innovation Solution

Implementing a separate debug pipeline and power domain for debugging features, which are only powered during debugging sessions, reducing energy consumption by isolating debug circuitry from the execution pipeline.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If debug circuitry is integrated into the execution pipeline, then debugging capabilities are available, but energy consumption increases continuously

Engineering Contradiction:
Improvedebugging capabilityVSAvoidenergy consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The processor is divided into separate power domains: a first power domain containing execution circuitry and a second power domain containing debug circuitry. This segmentation allows independent power control of each domain, enabling the debug pipeline to be powered off during normal execution while maintaining debugging capabilities when needed.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The power state of the debug pipeline is made dynamic rather than static. The second power domain can be selectively activated or deactivated based on whether debugging is required. This dynamic power management allows the system to transition between low-power execution mode and full-functional debug mode.

Inventive Principle:
Principle #15Dynamics

2Ease of operation

If debug pipeline is always powered, then debugging is always available, but power efficiency decreases

Engineering Contradiction:
Improvedebugging availabilityVSAvoidpower efficiency
Core Design Contradiction:
Ease of operationVSLoss of energy

Solution Approach 1:

Instead of continuous operation, the debug pipeline operates periodically or on-demand. The second power domain is activated only during debugging sessions and deactivated during normal processor execution, creating a periodic operation pattern that reduces overall energy consumption while maintaining debugging availability when needed.

Inventive Principle:
Principle #19Periodic action

Solution Approach 2:

Different parts of the processor have different power states. The first power domain (execution circuitry) operates continuously while the second power domain (debug circuitry) operates only when needed. This local differentiation of power quality allows the system to optimize overall power efficiency without compromising debugging capability.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS20250284606A1Processor with debug pipeline
Publication Date: 2025.09.11 TEXAS INSTRUMENTS INC
  • US20250284606A1 patent drawing
  • US20250284606A1 patent drawing

AI summary

An example system includes execution circuitry disposed within a first power domain; a sub-system to selectively operate to perform operations on the system and that is disposed within a second power domain that is separate from the first power domain; power control circuitry coupled to the sub-system; and detection circuitry coupled to the power control circuitry. The power control circuitry is configured to cause power to be supplied to the sub-system when the detection circuitry detects that the external component is coupled to the system, and configured to disable power supply to the sub-system when the detection circuitry detects that the external component is not coupled to the system.