Memory Debug Port Access Control for User Data and Key Protection
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Solution Overview
Problem
Memory devices face the risk of user data leakage when re-delivered to manufacturers due to unrestricted access, necessitating encryption and access control to prevent unauthorized exposure.
Innovation Solution
A memory device with a network-on-chip (NOC) and bus manager system that manages access to user data and encryption keys via a debug port, using classification information to allow or deny access based on the device's manufacturing stage and customer company permissions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If the debug port is opened to allow manufacturer access for error diagnosis, then the ease of operation is improved, but the security of user data and encryption keys deteriorates
Solution Approach 1:
The debug port's access permissions are made dynamic rather than static. The bus manager changes the accessibility state of the debug port based on the manufacturing stage classification information. During manufacturing stages, the debug port allows full access for diagnosis and debugging. After manufacturing is complete, the debug port's access is restricted or blocked entirely, preventing data leakage while still allowing error diagnosis when needed during the manufacturing phase.
2Ease of manufacture
If unlimited access is allowed to the memory device during manufacturing, then the ease of manufacture is improved, but the loss of information deteriorates
Solution Approach 1:
The system performs preliminary classification of the manufacturing stage before allowing any access through the debug port. The bus manager checks the classification information (such as manufacturing stage flags or status registers) before granting access permissions. This preliminary check ensures that unlimited access is only provided during actual manufacturing operations, and automatically revoked after manufacturing is complete, preventing any potential data leakage to unauthorized parties.
3Reliability
If the debug port is restricted to prevent data leakage, then the security of user data is improved, but the ease of operation deteriorates
Solution Approach 1:
The access control mechanism dynamically adjusts the debug port's permissions based on the current manufacturing stage. When the classification information indicates an active manufacturing stage, the bus manager enables full access for error diagnosis and debugging operations. When manufacturing is complete or the device is in a post-manufacturing state, the access is automatically restricted. This dynamic adjustment ensures that security restrictions are only applied when manufacturing is complete, eliminating unnecessary constraints on error diagnosis capability.
Data Source
AI summary
A memory device includes one or more non-volatile memories configured to store user data and at least one key related to the user data; a network-on-chip comprising a bus manager configured to manage access to the user data and the at least one key; and a debug port directly connected to a host and configured to receive a request from the host, wherein the bus manager is further configured to, based on the debug port being activated, determine whether to allow access of the host to the user data and the at least one key based on classification information.