Multi-chip Package Debug Ports for Embedded Signal Access
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Solution Overview
Problem
Troubleshooting multi-chip packages, particularly 2.5D and 3D IC packages, is challenging due to embedded I/O signals within silicon interposers, making it difficult to access and selectively measure conductive traces for debugging, unlike 2D IC packages where signals are easily accessible.
Innovation Solution
A microelectronic package with debug ports on its surface, coupled to semiconductor chips via an interposer, includes logical circuitry that selects and routes specific electrical contacts to these ports, allowing access to I/O signals between chips, even when they are embedded in the interposer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If multiple IC chips are mounted on a silicon interposer to form 2.5D or 3D IC packages, then the package size is reduced and signal propagation speed is improved, but the I/O signals become embedded and inaccessible for troubleshooting
Solution Approach 1:
The patent segments the I/O signals by providing separate access paths: normal operational signals remain embedded within the interposer, while debug signals are routed through dedicated debug ports on the package substrate. This segmentation allows simultaneous maintenance of compact packaging and accessible debugging capabilities.
Solution Approach 2:
The patent introduces debug ports as intermediary access points on the package substrate that mediate between the external debugging equipment and the embedded I/O signals. These ports serve as intermediaries that enable signal access without requiring physical access to the interposer interior.
2Power
If thousands of conductive traces are routed between chips in 2.5D/3D IC packages, then high-bandwidth communication is achieved, but the difficulty of selecting and measuring specific traces for troubleshooting increases
Solution Approach 1:
The patent segments the thousands of conductive traces into functional groups, with each debug port assigned to monitor specific groups of traces. This segmentation reduces the complexity by organizing traces into manageable categories that can be selectively accessed through corresponding debug ports.
Solution Approach 2:
The system provides self-service debugging capability where the debug ports automatically route and present the selected trace signals for measurement without requiring manual intervention to physically access or identify specific traces among thousands of interposer connections.
3Ease of operation
If 2D IC packages are used with discrete chip mounting, then troubleshooting is straightforward with accessible conductive traces, but the package is larger, heavier, and slower
Solution Approach 1:
The patent introduces debug ports as intermediary access points that preserve the troubleshooting ease of 2D packages while maintaining the compact 2.5D/3D architecture. These intermediaries provide signal access similar to accessible traces in 2D packages without requiring the physical layout characteristics of 2D mounting.
Solution Approach 2:
The patent adds a new dimension of accessibility by placing debug ports on the package substrate surface, creating a third dimension of signal access beyond the traditional chip-to-chip interposer plane. This dimensional addition enables troubleshooting without compromising the vertical stacking benefits of 2.5D/3D packages.
Data Source
AI summary
A microelectronic package has an IC chip that includes logical circuitry for routing certain I/O signals to debug ports disposed on an outer surface of the microelectronic package. The I/O signals include data and command signals that are transmitted between semiconductor chips in the microelectronic package via conductive traces that are not physically accessible via with conventional debugging techniques. The logical circuitry may be configured to programmably select I/O signals based on a software input, and may be connected to the various I/O signals transmitted between the IC chip and another IC chip in the microelectronic package when a debugging of the I/O signals is enabled. Circuitry employed in conventional operation of the IC chip may also be employed to connect the logical circuitry to the various I/O signals.