Debug Registers for Halting Processor Cores After Reset
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Solution Overview
Problem
Current debugging mechanisms for integrated circuits, such as JTAG, lack the ability to effectively halt processor cores before instruction execution, especially in systems that frequently put processors to sleep and awaken them, making it difficult to debug boot-up sequences and initial states.
Innovation Solution
Incorporating a debug port with a power management unit and registers that allow external debuggers to program a halt signal to be asserted upon processor reset, enabling processors to halt operation prior to executing instructions, thus allowing debugging from a known reference point.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If processors are frequently put to sleep and awakened, then power consumption is reduced, but the ability to debug boot-up sequences and initial states is lost
Solution Approach 1:
The patent applies preliminary action by setting the halt register before the processor is reset or awakened from sleep. The debugger programs the register in advance, and the processor automatically halts at the designated instruction when it resumes execution, enabling debugging of boot-up sequences without requiring the processor to remain powered on continuously.
Solution Approach 2:
The patent introduces a halt register as an intermediary mechanism between the debugger and the processor. This register acts as a mediator that stores the address of the instruction where the processor should halt, allowing the debugger to control processor execution state indirectly even when the processor is in sleep mode or has been reset.
2Reliability
If processors are reset frequently, then system stability is improved, but debugging of initial execution states becomes difficult
Solution Approach 1:
The patent applies preliminary action by pre-configuring the halt register with the desired instruction address before the reset operation. This ensures that when the processor exits reset, it will automatically halt at the specified location, preserving debugging capability despite frequent reset operations that improve system stability.
Solution Approach 2:
The patent implements feedback by allowing the debugger to read the processor state after halting and to modify the halt register accordingly. This feedback loop enables the debugger to control and observe processor behavior through multiple reset cycles, maintaining debugging information availability while allowing frequent resets for system stability.
3Ease of operation
If debug registers are programmed before reset, then halting capability is enabled, but the register programming must be preserved through power management states
Solution Approach 1:
The patent uses the halt register as an intermediary that can be programmed by the debugger and then maintained through power management transitions. The register acts as a stable storage element that preserves the halt address information even when the processor enters sleep mode or is reset, allowing the halt capability to be maintained without continuous power or active programming.
Data Source
AI summary
A method and apparatus of stopping a functional block of an integrated circuit (IC) for debugging purposes is disclosed. In one embodiment, an IC includes a number of functional units accessible by an external debugger via a debug port (DP). During a debug operation, a power controller in the IC may power down a functional unit. When the functional unit is powered off, a first register may be programmed. Responsive to the programming of the first register, a first signal may be asserted and provided to the functional unit. When power is restored to the functional unit, operation of the functional unit may be halted prior to execution of instructions or other operations, responsive to the signal.