Debug Reset Retains Trace Buffer Data in SoC
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Solution Overview
Problem
Debugging complex system-on-chips (SoCs) is challenging due to the erasure of critical failure information during reset operations, making it difficult to diagnose issues such as PCIe card failures, as conventional reset methods erase the events leading to the failure.
Innovation Solution
A distributed debugging system with multiple debug units associated with each functional unit, allowing for a debug reset that retains information in trace buffers while clearing it during power-up resets, using SRAM for storage and synchronization with global timestamp counters to maintain data integrity across resets.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional reset operation is performed to reset the system, then the system is restored to initial state, but the debug information in trace buffers is erased making debugging difficult
Solution Approach 1:
The system segments the reset operation into two distinct types: power-up reset and debug reset. Power-up reset clears all resources including trace buffers, while debug reset clears only functional units but preserves trace buffer contents. This segmentation allows selective resetting that maintains debug information when needed.
Solution Approach 2:
The debug reset operation applies different reset behavior to different parts of the system: functional units are cleared while trace buffers retain their data. This local quality approach ensures that only the necessary components are reset while preserving critical debug information in specific memory regions.
2Ease of operation
If trace buffer information is retained across resets for debugging, then debugging capability is improved, but system complexity increases due to multiple reset types
Solution Approach 1:
The reset controller is designed with multi-functionality to handle both power-up reset and debug reset operations through a unified interface. The same reset controller that manages power-up resets also manages debug resets, reducing the need for separate control logic and minimizing the increase in system complexity.
Solution Approach 2:
The reset controller acts as an intermediary between the processor and various system resources. It receives reset commands from the processor, determines the appropriate reset type based on the command, and selectively resets functional units while preserving trace buffer contents. This intermediary approach simplifies the overall system architecture by centralizing reset management.
3Loss of information
If non-volatile memory is used to store debug information, then information retention is improved, but manufacturing cost increases
Solution Approach 1:
The system uses volatile SRAM for trace buffers instead of expensive non-volatile memory. The trace buffers are designed to be temporary storage that can be selectively preserved or cleared based on reset type. This approach uses inexpensive memory technology while achieving the desired information retention through clever control logic rather than expensive hardware.
Data Source
AI summary
An integrated circuit can include a functional unit and a local debug unit. The local debug unit can include a trace buffer, and the local debug unit is configured to track and store operation information of the functional unit in the trace buffer. The integrated circuit can also include a global debug unit coupled to the local debug unit. The integrated circuit is configured to send a debug reset command to reset the functional unit, without sending the debug reset command to the local debug unit, thereby retaining information stored in the trace buffer. The integrated circuit is also configured to send a power-up reset command to reset the local debug unit and the functional unit, thereby causing the local debug unit to clear the trace buffer.