Debugging Circuit Stack Access Trace Compression

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Solution Overview

Problem

Conventional debugging systems fail to distinguish between stack access and normal data access, leading to unnecessary data output and increased resource utilization, and do not effectively utilize the locality and continuity of stack access addresses for compression.

Innovation Solution

The debugging system independently monitors and outputs stack access and normal data access information, using absolute and relative values to generate trace information, allowing for selective tracing and compression based on the characteristics of stack access.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of information

If the debugging circuit outputs all data access information including both stack access and normal data access, then the trace information is complete, but the amount of trace information increases and bandwidth is wasted

Engineering Contradiction:
Improvetrace information completenessVSAvoidamount of trace information
Core Design Contradiction:
Loss of informationVSQuantity of substance

Solution Approach 1:

The patent segments data access information into two distinct types: stack access information and normal data access information. The debugging circuit independently monitors and outputs these two types separately, allowing selective tracing. This segmentation enables the system to output only the necessary trace information without including unnecessary data, thereby reducing the amount of trace information while maintaining completeness of relevant data.

Inventive Principle:
Principle #1Segmentation

2Loss of information

If the debugging circuit monitors and outputs all data access information, then no trace information is lost, but bandwidth efficiency decreases due to unnecessary data output

Engineering Contradiction:
Improvetrace information completenessVSAvoidbandwidth efficiency
Core Design Contradiction:
Loss of informationVSProductivity

Solution Approach 1:

The patent extracts stack access information from the overall data access information. The debugging circuit is configured to independently output stack access information separately from normal data access information. This extraction allows the system to remove unnecessary normal data access information from the output stream, thereby improving bandwidth efficiency by transmitting only the essential stack access trace information that is critical for debugging.

Inventive Principle:
Principle #2Taking out (Extraction)

3Ease of operation

If the debugging circuit treats stack access and normal data access as the same trace information, then the monitoring process is simple, but the device complexity increases due to larger storage requirements

Engineering Contradiction:
Improvemonitoring process simplicityVSAvoidstorage unit capacity
Core Design Contradiction:
Ease of operationVSDevice complexity

Solution Approach 1:

The patent segments trace information handling into separate processing paths for stack access and normal data access. By independently outputting stack access information, the system avoids the need for large storage units that would be required to store all data access information. This segmentation maintains monitoring simplicity while reducing storage requirements and device complexity.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS7873875B2Debugging system, debugging circuit and information processing apparatus
Publication Date: 2011.01.18 MONTEREY RESEARCH LLC
  • US7873875B2 patent drawing
  • US7873875B2 patent drawing
  • US7873875B2 patent drawing

AI summary

A debugging system includes a CPU that is a debugging target and a debugging circuit. The CPU has an output part configured to independently output stack access information of a stack access and data access information of a data access excluding the stack access, as data access information of the CPU that is monitored by the debugging circuit. The debugging circuit has a trace part configured to independently generate and output trace information of the stack access from the stack access information that is output from the CPU and trace information of the data access excluding the stack access from the data access information that is output from the CPU.