Debug Interface Switching Circuit for Multiple Master Arbitration
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Solution Overview
Problem
Current debugging and testing technologies, such as JTAG, are limited by allowing only a single master device on a debug bus, restricting the availability of debug and test connections, especially in systems with multiple components, and lack clear termination methodologies, leading to incompatibilities between device vendors.
Innovation Solution
A switching circuit is introduced to switch mastership between devices, enabling any device to obtain mastership and communicate with others, and a debug and test access port is adapted to support multiple connections, allowing peer-to-peer data exchange and flexible debug network configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a single master device is allowed on a debug bus, then the debug bus protocol is simple to implement, but the availability of debug and test connections is restricted in systems with multiple components
Solution Approach 1:
The patent implements dynamic master arbitration where any device on the debug bus can contend for and become the master through arbitration logic. This dynamic approach allows multiple devices to take turns being masters, increasing adaptability while maintaining a relatively simple base protocol structure that handles master transitions automatically.
Solution Approach 2:
The patent introduces arbitration logic as an intermediary mechanism that mediates between multiple devices wanting to be masters. This arbitration layer handles the complexity of master management, allowing the underlying debug bus protocol to remain relatively simple while supporting multiple potential masters through the intermediary arbitration process.
2Adaptability or versatility
If a dedicated debug and test access port is used, then debugging and testing capabilities are provided, but the number of connections is limited and peer-to-peer data exchange is restricted
Solution Approach 1:
The patent makes the debug and test access port universal by allowing any device to become a master and initiate debug operations. The access port structure is designed to handle both traditional dedicated master connections and peer-to-peer connections, making it multi-functional and adaptable to different debugging scenarios without requiring separate dedicated structures.
Solution Approach 2:
The patent segments the debug network into multiple potential master nodes, each capable of independent operation. This segmentation allows any device to function as a master for its connected devices, enabling flexible peer-to-peer debugging while maintaining the overall network structure through standardized access port interfaces.
3Reliability
If clear termination methodologies are not defined, then device vendor compatibility is improved through flexibility, but incompatibilities arise between device vendors
Solution Approach 1:
The patent defines specific parameter changes and state transitions for master arbitration and termination. By standardizing these parameters (such as arbitration outcomes, master state transitions, and connection termination protocols), the patent ensures that devices from different vendors can interoperate reliably while maintaining the flexibility needed for various debugging configurations.
Data Source
AI summary
Methods and apparatuses relating to a multiple master capable debug interface are described. In one embodiment, an apparatus includes a device circuit, a wireless connector circuit, and a switching circuit coupled between the device circuit and the wireless connector circuit to switch a debug and test mastership from the wireless connector circuit to a debug and test tool, wirelessly connected to the wireless connector circuit, to perform a debug and test operation on the device circuit.