Debug System Integrating Break Point and Branch Trace Mechanisms

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Solution Overview

Problem

Existing debug systems for semiconductor devices face complexity in processing due to the need for separate branch trace and break point detection mechanisms, leading to complicated circuit configurations and increased debug support program scale.

Innovation Solution

A debug system that integrates break point detection and branch trace mechanisms by using a HW break circuit with a first register for the execution start address, a second register for the minimum break point address, and a counter to manage interruptions based on comparison results, allowing for simplified circuit configurations and reduced program scale.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If separate branch trace and break point detection mechanisms are used, then effective program execution control is achieved, but circuit configuration becomes complicated

Engineering Contradiction:
Improveprogram execution controlVSAvoidcircuit configuration
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent combines the break point detection mechanism and branch trace mechanism into a single integrated circuit. The break point determination unit and branch determination unit share common resources including the program counter, comparison logic, and interruption control, thereby achieving effective program execution control while simplifying the circuit configuration compared to having separate independent mechanisms.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The interruption determination unit performs multiple functions: it determines both break point conditions (by comparing program counter with break point addresses) and branch conditions (by analyzing branch instructions). This multi-functional approach allows a single circuit to provide both break point detection and branch trace capabilities, reducing overall system complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Adaptability or versatility

If separate branch trace and break point detection mechanisms are used, then comprehensive debugging capability is achieved, but debug support program scale increases

Engineering Contradiction:
Improvedebugging capabilityVSAvoidprogram scale
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The debug support program implements a unified debugging mechanism that combines break point detection and branch tracing functions. By merging the operational logic into a single integrated flow within the interruption determination unit, the program scale is reduced while maintaining comprehensive debugging capability through shared determination routines.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The interruption determination unit is designed to handle multiple debugging scenarios (break points and branch traces) through a single multi-functional module. This universal approach allows the debug support program to maintain versatility in debugging capabilities while minimizing program scale by avoiding duplicate code for separate mechanisms.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS10496521B2Debug system and semiconductor device
Publication Date: 2019.12.03 RENESAS ELECTRONICS CORP
  • US10496521B2 patent drawing
  • US10496521B2 patent drawing
  • US10496521B2 patent drawing

AI summary

When a program counter value during execution of a target program is an execution start address or less or is larger than the execution start address and is equal to or larger than minimum address among a plurality of addresses associated with a plurality of break points, a break circuit interrupts an execution of the target program, and during the interruption of the execution of the target program, and when the program counter value does not match with anyone of the plurality of break points, a debug control unit sets the program counter value as the execution start address to a first register, sets to a second register an address that is larger than the program counter value and is minimum among the plurality of break points as the minimum address, and resumes the execution of the target program from the execution start address.