Debug Timestamping via Counter Reset for Embedded Systems
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Solution Overview
Problem
Debugging tools face challenges in balancing functionality and timestamp resolution with the limited resources and perturbance effects on embedded systems, particularly in fully target-based tools and host-target based tools with limited time-stamping functionality.
Innovation Solution
A method and processor configuration that generates timestamps by periodically incrementing a counter on the target processor, allowing implicit resetting and storing values in a software-accessible location, reducing resource usage and perturbance, and enabling efficient compression and transmission of timestamp data.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If fully target-based debugging tools are used to gather and display debugging information on the target system, then debugging functionality is provided, but the target system resources (memory, CPU, I/O) are consumed and the debugee may be perturbed
Solution Approach 1:
The patent extracts the debugging tool execution environment from the target system to a host system. The host system runs the debug tool and communicates with the target via a debug link, thereby extracting the resource-consuming debugging operations away from the target system while maintaining full debugging functionality.
Solution Approach 2:
The patent introduces a debug link as an intermediary communication channel between the host system and target system. This intermediary allows the host-based debug tool to access target execution information without requiring direct resource consumption on the target, enabling debugging while preserving target resources.
2Quantity of substance
If host-target based debugging tools are used to execute the debug tool on a separate host computer, then target system resources are preserved and perturbance is reduced, but time-stamping functionality and resolution may be limited
Solution Approach 1:
The patent implements self-service time-stamping by providing dedicated timestamp instructions that execute directly on the target processor. These instructions automatically generate precise timestamps using the target's own clock resources, making the time-stamping service available to the debug tool without consuming additional target resources or limiting resolution.
Solution Approach 2:
The patent makes the target processor's clock resource serve multiple functions: it continues to drive normal processor operation while simultaneously providing high-resolution time-stamping service for debugging. The timestamp instructions access the same clock resources that the processor uses for its own timing, achieving multi-functionality without additional hardware.
3Measurement precision
If high-resolution timestamps are generated using target processor clock cycles, then measurement precision is improved, but the target system experiences increased perturbance and resource consumption
Solution Approach 1:
The patent extracts the burden of timestamp processing from the target processor by providing dedicated timestamp instructions that operate independently. These instructions capture clock cycle counts directly into registers without requiring general-purpose processor intervention, thereby extracting the perturbance away from the debugee while maintaining high resolution.
Solution Approach 2:
The patent creates a copy of the clock cycle count value into dedicated timestamp registers through specialized instructions. This copying mechanism captures the timing information without requiring the processor to execute general timing routines, minimizing perturbance to the debugee while preserving full timestamp resolution.
Data Source
AI summary
A method and processor for debugging a target processor. The method comprises: executing code on the target processor to generate trace information for debugging; and during execution of that code, periodically incrementing a value of a counter on the target processor. The execution of the code includes executing a plurality of timestamp instructions on the target processor each to associate a respective timestamp with the trace information. The execution of each timestamp instruction comprises generating the respective timestamp by reading the value of the counter into a software accessible storage location and subsequently resetting the counter.