On-Chip Debug Trace Buffer for Program Counter Discontinuity
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Solution Overview
Problem
Highly integrated digital signal processing systems face challenges in testability, observability, and controllability due to shrinking interconnect pitch and increased complexity, leading to reduced visibility and control, longer design cycles, and increased costs, with traditional debug methods becoming inadequate for modern systems-on-a-chip.
Innovation Solution
The implementation of on-chip debug facilities with configurable emulation capabilities, including real-time emulation, trace, and advanced analysis, which allow for adjustable debug resources and scalable tool deployment, enabling better visibility and control through customizable debug pin utilization and efficient data exchange.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If higher integration levels and increased on-chip memory are used, then system performance and footprint density are improved, but design time and test development time are increased
Solution Approach 1:
The patent applies preliminary action by pre-configuring multiple on-chip debug facilities (trace buffers, control registers, interrupt handlers) during the chip design phase. These facilities are prepared in advance to capture program counter changes, trace data, and debug information before actual debugging is needed, thereby reducing design time and enabling faster debugging of high-performance systems.
2Ease of operation
If scan based emulation is implemented, then debug capability is improved, but electrical intrusiveness and connectivity issues are increased
Solution Approach 1:
The patent extracts the debugging functionality from external scan-based emulation equipment and implements it directly on-chip through dedicated debug facilities. This includes on-chip trace buffers, control registers, and interrupt handlers that operate independently within the processor, eliminating the need for external scan chains and reducing electrical intrusiveness while maintaining full debug capability.
3Loss of information
If more on-chip debug facilities are provided, then visibility and control are improved, but chip area and cost are increased
Solution Approach 1:
The patent implements multi-functional on-chip debug facilities that serve multiple purposes. The trace buffer system can capture program counter changes, data transfers, and instruction execution. The same infrastructure supports both real-time debugging and post-mortem analysis. Control registers and interrupt handlers are designed to handle multiple debug scenarios, maximizing the utility of each bit of silicon real estate allocated to debugging.
4Device complexity
If traditional debug methods are used, then simplicity is maintained, but detectable fault coverage is reduced
Solution Approach 1:
The patent introduces an intermediary on-chip trace buffer system that mediates between the processor core and external debugging equipment. This intermediary captures program counter changes and trace data at the source, providing comprehensive fault coverage without requiring complex external test equipment. The trace buffer acts as a buffer that simplifies the interface between the complex processor and the debugger, maintaining simplicity while enhancing fault detection capability.
Data Source
AI summary
This invention tracks emulation changes in the program counter of the central processing unit of a data processor during emulation halt. The sequence includes: pausing the central processing unit in response to an emulation halt; employing the emulator to change the program counter. In this case when the central processing unit resumes operation, there will be a discontinuity in the program counter. The trace data will show a change in the program counter address. This invention uses a unique exception signal similar to those used to mark interrupts to inform the user that this program counter discontinuity is due to an emulation change of the program counter during emulation halt.