Debugging Circuit Preventing CPU Execution During Preparation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In central processing systems, the transition from normal operational mode to debugging mode is lengthy, causing potential execution of programs during debugging preparation, leading to unpredictable operations and unnecessary peripheral circuit activation.
Innovation Solution
A method and circuit that generate mode judgment and monitoring signals to prevent the central processing unit from executing programs during debugging preparation, using a mode judgment circuit, monitoring circuit, and selection circuit to control data bus access and ensure proper debugging operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If the CPU operates in normal operational mode and switches to debugging operation mode through JTAG interface, then debugging function is enabled, but it takes a long time to complete debugging preparation from inputting command signals to test access ports till inputting command signals to control register
Solution Approach 1:
The patent applies preliminary action by generating a mode judgment signal immediately when reset is canceled and before debug data is received, to proactively prevent program execution during the debugging preparation phase. This early intervention stops the CPU from executing instructions during the lengthy JTAG command input process, resolving the time loss issue while maintaining debugging functionality.
2Productivity
If the CPU executes program during debugging preparation, then program execution occurs, but unpredictable operations and unnecessary peripheral circuit activation occur
Solution Approach 1:
The patent applies preliminary anti-action by using the mode judgment signal to preemptively block program execution during debugging preparation. The monitoring signal generated from this mode judgment signal actively prevents the CPU from executing instructions or accessing peripheral circuits during the vulnerable preparation phase, thereby eliminating unpredictable operations and ensuring debugging reliability before actual debugging begins.
Data Source
AI summary
In a debugging circuit and a controlling method of the debugging circuit, a mode judgment signal is generated which indicates that a central processing unit (CPU) is preparing to debug a predetermined program. Responsive to the mode judgment signal, a monitoring signal is generated indicative of an attempt by the CPU to execute the predetermined program during the debugging preparation. Furthermore, a transfer of an instruction code corresponding to the predetermined program is controlled so that the CPU is prevented from executing the predetermined program during the debugging preparation, responsive to the monitoring signal. Alternatively, in the debugging circuit and the method, instead of controlling the transfer of the instruction code responsive to the monitoring signal, another instruction code may be transferred to the CPU, responsive to the mode judgment signal. The another instruction code prevents the CPU from executing the predetermined program during the debugging preparation.