Debuss Holes for Semiconductor Package Substrate Testing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional semiconductor packaging methods face challenges in efficiently decoupling and testing bussed traces on packaging substrates before singulation, leading to potential electrical shorts and increased manufacturing costs due to the complexity of integrating high-value components like DRAM stacks with diverse cost structures.
Innovation Solution
The method involves forming debuss holes at intersections of bussed traces, electrically testing the decoupled traces, and singulating the substrates using mechanical or laser drilling, allowing for pre-singulation identification of good or defective substrates, thereby reducing costs and improving yields.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If bussed traces are used for metal plating regions on packaging substrates, then manufacturing efficiency is improved, but electrical shorts between traces may occur and testing becomes difficult
Solution Approach 1:
The patent forms debuss holes at intersections of bussed traces before final singulation to prevent electrical shorts. This preliminary action eliminates potential reliability issues before they can affect final product performance, allowing efficient bussed trace plating while maintaining electrical connection reliability.
Solution Approach 2:
The patent segments the continuous bussed traces by forming debuss holes at intersections, effectively dividing the trace network into isolated segments. This segmentation prevents electrical shorts between different trace regions while maintaining the manufacturing efficiency benefits of bussed traces during the plating process.
2Ease of manufacture
If substrates are singulated after metal plating, then component integration is simplified, but defective substrates cannot be identified before final assembly
Solution Approach 1:
The patent performs electrical testing after forming debuss holes but before final singulation. This preliminary testing identifies defective substrates early in the process, allowing removal of bad substrates before costly final assembly. This maintains ease of manufacture while improving manufacturing yield by preventing assembly of defective units.
Solution Approach 2:
The patent introduces an intermediate testing stage between plating and singulation by forming debuss holes. This intermediary step enables electrical characterization of substrates before final commitment to assembly, serving as a quality gate that improves yield without complicating the overall manufacturing flow.
3Difficulty of detecting and measuring
If debuss holes are formed at trace intersections, then electrical testing becomes possible, but additional manufacturing steps are required
Solution Approach 1:
The patent combines the formation of debuss holes with the existing singulation process by locating holes at intersections that align with saw streets. This merging of functions allows electrical testing capability to be added without requiring separate processing steps, thereby reducing the increase in process complexity while enabling electrical testing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables effective electrical testing and separation of circuits before singulation, reducing manufacturing costs and improving yield by allowing for selective processing and assembly of high-value components, and facilitating the integration of diverse cost structures like DRAM stacks within semiconductor packaging.
Implementation Method 1
The regions of the packaging substrate may be metal plated utilizing an electroplating process
Implementation Method 2
The holes may be formed utilizing lasing
Data Source
AI summary
Methods for temporary bussing of semiconductor package substrates are disclosed and may include metal plating regions of a packaging substrate utilizing a plurality of bussed traces, which may be decoupled by forming debuss holes at intersections of the bussed traces. The decoupled traces may then be electrically tested, and the packaging substrate may be singulated into a plurality of substrates utilizing a sawing process through singulation areas in the packaging substrate. The traces may be electrically coupled via plating bars in the substrate. The plating bars may be located in the singulation areas. The intersections of the bussed traces may be in a Y pattern, which may be repeated along the singulation areas. The debuss holes may be formed utilizing mechanical drilling or lasing. The regions of the packaging substrate may be metal plated utilizing an electroplating process. The plurality of bussed traces may be biased for the electroplating process.