Decentralized Power Management for Multi-Core Processors
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Solution Overview
Problem
Current multi-core microprocessor designs face challenges in power management due to the need for centralized hardware coordination logic, which can lead to complex, less symmetric die designs and scaling issues, as well as reliance on system software for inter-core coordination, limiting flexibility and efficiency in implementing restricted operational states.
Innovation Solution
A decentralized power management system where each core participates in a sideband communication-based inter-core state discovery process, using synchronization logic to coordinate and implement more restrictive operating states without centralized non-core logic, allowing for efficient power state management and reduced die size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If centralized hardware coordination logic is used to manage power states across multiple cores, then power management coordination is achieved, but die design complexity increases and manufacturing yield decreases
Solution Approach 1:
The invention extracts the centralized coordination logic from non-core hardware and relocates it to software execution within the cores themselves. Each core runs a state discovery routine that coordinates power state transitions through inter-core communication, eliminating the need for separate centralized hardware coordination logic and thereby reducing die area and improving manufacturing yield.
Solution Approach 2:
The cores perform self-service coordination by executing power state discovery routines locally. Each core independently determines whether it can transition to a restricted power state by checking if all other cores are also ready, using local inter-core communication interfaces. This self-organized approach eliminates the need for centralized coordination hardware.
2Adaptability or versatility
If system software is used for inter-core coordination, then flexibility in power state management is maintained, but coordination efficiency and responsiveness are limited
Solution Approach 1:
The invention introduces an intermediary layer of synchronized state discovery routines that run on each core and coordinate power state transitions. These routines use inter-core communication to synchronize readiness status across all cores, enabling efficient and flexible power state management without relying solely on system software.
Solution Approach 2:
The state discovery routine performs preliminary coordination actions by having each core independently determine its readiness for restricted power states before any actual state transition occurs. This preliminary synchronization of readiness status across all cores enables efficient and responsive power state management.
Data Source
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AI summary
A multi-core processor provides a configurable resource shared by two or more cores, wherein configurations of the resource affect the power, speed, or efficiency with which the cores sharing the resource are able to operate. Internal core power state management logic configures each core to participate in a de-centralized inter-core power state discovery process to discover a composite target power state for the shared resource that is a most restrictive or power-conserving state that will not interfere with any of the corresponding target power states of each core sharing the resource. The internal core power state management logic determines whether the core is a master core authorized to configure the resource, and if so, configures that resource in the discovered composite power state. The de-centralized power state discovery process is carried out between the cores on sideband, non-system bus wires, without the assistance of centralized non-core logic.