Decentralized Power State Coordination for Multi-Core Processors
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Solution Overview
Problem
Multi-core microprocessors face challenges in power management due to the need for centralized hardware coordination logic, which can lead to complex, asymmetric die designs and scaling issues, as well as reliance on system software for inter-core coordination, limiting flexibility and efficiency in power state synchronization.
Innovation Solution
A decentralized power management system where each core has its own coordination logic to set and implement a target operating state, using sideband connections and hierarchical coordination systems to synchronize power states without reducing performance of other cores, thereby enabling independent power state management across multiple cores.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If centralized hardware coordination logic is used for power management, then power state synchronization can be achieved, but die design complexity increases and manufacturing yield decreases
Solution Approach 1:
The patent segments the centralized coordination logic into distributed components by implementing power state coordination at the core level. Each core includes its own power state coordination logic that independently manages power states, eliminating the need for a single centralized coordination logic block and thereby reducing die design complexity while maintaining synchronization reliability.
Solution Approach 2:
The patent extracts the power state coordination functionality from a centralized location and distributes it across multiple cores. By taking out the coordination logic from a single centralized block and embedding it in each core, the patent reduces the complexity of any single die design and improves manufacturing yield while preserving the ability to synchronize power states across the multi-core processor.
2Adaptability or versatility
If system software is used for inter-core coordination, then implementation flexibility is maintained, but coordination efficiency and response time are reduced
Solution Approach 1:
The patent implements self-service by enabling each core to autonomously manage its own power state without requiring system software intervention. Each core includes integrated power state coordination logic that can independently determine and execute power state transitions, thereby improving coordination efficiency and response time while maintaining implementation flexibility through hardware-enforced protocols.
Solution Approach 2:
The patent replaces the software-based coordination mechanism with a hardware-based power state coordination system. By substituting the mechanical/software coordination approach with hardware-level logic embedded in each core, the patent achieves faster response times and higher coordination efficiency while preserving flexibility through hardware-defined power state management protocols.
3Reliability
If all cores must be ready before chipset disables bus clock, then power management can be implemented, but system response time increases
Solution Approach 1:
The patent applies preliminary action by having each core independently prepare for power state transitions before the actual transition occurs. Each core's power state coordination logic proactively reads its target power state and prepares necessary internal states, allowing the chipset to disable the bus clock sooner without waiting for all cores to be manually ready, thereby reducing system response time while maintaining reliable power management.
Solution Approach 2:
The patent introduces dynamics by enabling asynchronous power state preparation across cores. Instead of a static requirement where all cores must be ready before clock disablement, the system dynamically allows cores to prepare at different rates and times, with the chipset coordinating based on actual core readiness states. This dynamic approach reduces the time loss associated with sequential preparation while ensuring reliable power management implementation.
Data Source
AI summary
A multi-core microprocessor is organized into a plurality of resource-associated domains including core domains, group domains, and a global domain. Each domain relates to either local resources, group resources, or global resources that are respectively used by a single core, a group of cores, or all the cores. Each core has its own independently settable target operating state selected from a plurality of possible target operating states that designate configurations for the local resources, group resources, and global resources. Each core is provided with coordination logic configured to implement or request implementation of the core's target operating state, but only to the extent that implementation of the target operating state would not reduce performance of any other core below its own target operating state.