Decimal Floating-Point Divider Using Newton-Raphson Iteration
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Solution Overview
Problem
Current microprocessors lack support for decimal floating-point arithmetic, leading to time-consuming and error-prone conversions between decimal and binary numbers, which is unacceptable in applications like financial analysis and banking where accuracy is critical.
Innovation Solution
A processing unit employing piecewise linear approximation and modified Newton-Raphson iteration for decimal floating-point division, reducing memory requirements and improving reciprocal estimation, followed by efficient rounding to produce accurate decimal floating-point quotients.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If software is used to perform decimal floating-point arithmetic, then accuracy is improved by eliminating conversion errors, but execution time increases significantly (100 to 1,000 times slower)
Solution Approach 1:
The patent replaces software-based decimal arithmetic with a dedicated hardware decimal floating-point divider that uses Newton-Raphson iteration. This hardware implementation performs decimal division directly without binary conversion, achieving both high accuracy and fast execution speed, thereby resolving the contradiction between accuracy and productivity.
Solution Approach 2:
The patent changes the fundamental parameter of number representation by implementing native decimal floating-point support in hardware, allowing direct processing of decimal numbers without conversion to binary. This parameter change enables both accurate decimal arithmetic and efficient execution by eliminating the slow conversion step inherent in software implementations.
2Productivity
If binary floating-point arithmetic is used to process decimal data, then execution speed is improved, but measurement precision deteriorates due to conversion errors
Solution Approach 1:
The patent substitutes the binary floating-point arithmetic system with a dedicated decimal floating-point hardware divider. This replacement eliminates the need for decimal-to-binary conversion while maintaining fast execution speeds through hardware acceleration, thereby preserving both productivity and measurement precision.
Solution Approach 2:
The patent introduces a decimal floating-point divider as an intermediary component between decimal data and processing operations. This intermediary handles decimal arithmetic natively, avoiding the harmful conversion step while enabling efficient processing, thus resolving the precision-speed tradeoff.
3Ease of manufacture
If fixed-point decimal dividers are used, then hardware support is provided, but adaptability deteriorates because scaling must be manually performed for different magnitudes
Solution Approach 1:
The patent implements a dynamic scaling mechanism within the decimal floating-point divider that automatically adjusts to handle different number magnitudes. The hardware structure includes components that dynamically manage the decimal point position and scaling factors, eliminating the need for manual scaling operations while maintaining adaptability across various data ranges.
Solution Approach 2:
The patent designs a universal decimal floating-point divider that can handle both fixed-point and floating-point decimal operations. The hardware structure is engineered to perform multiple functions including division, scaling, and magnitude adjustment, thereby providing both hardware support and adaptability to different number formats and magnitudes.
4Quantity of substance
If piecewise linear approximation with decimal encoding is used, then memory requirements are reduced, but device complexity increases due to operand modification requirements
Solution Approach 1:
The patent employs parameter changes through decimal encoding schemes that transform the dividend and divisor into a normalized format suitable for efficient division. By changing the representation parameters of the operands, the system reduces memory requirements while the accompanying operand modification operations are optimized to minimize overall complexity.
Solution Approach 2:
The patent segments the division process into distinct stages: operand modification, piecewise linear approximation, and Newton-Raphson iteration. This segmentation allows each stage to be optimized independently, reducing memory requirements in the approximation stage while managing complexity through structured processing of operand modifications in separate stages.
Data Source
AI summary
A decimal floating-point divider is described that implements efficient hardware-based techniques for performing decimal floating-point division. The divider uses an accurate piecewise linear approximation to obtain an initial estimate of a divisor's reciprocal. The divider improves the initial estimate of the divisor's reciprocal using a modified form of Newton-Raphson iteration. The divider multiplies the estimated divisor's reciprocal by the dividend to produce a preliminary quotient. The preliminary quotient is rounded to produce the final decimal floating-point quotient.