Decimal Floating-Point ISA for Single-Cycle Format Conversion
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Solution Overview
Problem
Conventional digital processors are inadequate for handling large floating-point data sets in human-readable decimal character sequences due to the need for explicit conversion to IEEE 754-formatted binary representations, leading to high latency and inefficiency in computations.
Innovation Solution
A universal floating-point Instruction Set Architecture (ISA) that enables direct computation with long decimal character sequences up to 128 characters in length, eliminating the need for explicit conversion by using memory-mapped operators with private result buffers and a 'mover'-style architecture that pushes and pulls data in a single clock cycle, without opcodes, allowing for simultaneous execution of dual operands and automatic conversion between formats.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional architectures load and convert decimal character sequences to IEEE 754 binary format, then computation can be performed, but the conversion process requires thousands of clock cycles causing high latency
Solution Approach 1:
The patent replaces the conventional mechanical conversion process (loading characters sequentially into 64-bit registers and converting through thousand+ clock cycles) with a specialized hardware system that processes entire decimal character sequences in parallel. The convertFromDecimalCharacter operator accepts up to 128 bytes of decimal data and converts it to binary64 format in a single clock cycle, substituting the step-by-step mechanical conversion with a dedicated hardware transformation engine.
Solution Approach 2:
The invention changes the fundamental parameters of the conversion process by implementing a hardware operator that processes 128 bytes of decimal character data in one clock cycle, compared to the conventional approach that processes 8 bytes at a time over thousands of cycles. This parameter change in data width and processing throughput directly reduces conversion latency from thousands of cycles to a single cycle.
2Productivity
If interleaving multi-threading is used to hide conversion latency, then some parallelism is achieved, but the pipeline still stalls for 22 clocks per conversion waiting for completion
Solution Approach 1:
The patent substitutes the software-based interleaved multi-threading approach with a hardware-based solution where the convertFromDecimalCharacter operator performs the entire conversion in one clock cycle. This eliminates the need for complex thread management and pipeline stall handling, as the conversion completes before the next instruction needs to execute, removing the 22-clock stall entirely.
3Loss of time
If 30 threads are created to completely hide 30-clock latency, then latency is hidden, but the processor requires 30 program counters, stack pointers, and register sets creating logic bloat and making debugging extremely difficult
Solution Approach 1:
The patent replaces the complex 30-thread architecture with a single-threaded design where the convertFromDecimalCharacter operator completes conversion in one clock cycle. This substitution eliminates the need for 30 sets of program counters, stack pointers, and registers, dramatically reducing logic bloat and simplifying debugging while achieving the same latency hiding effect.
Solution Approach 2:
The invention performs the conversion action preliminarily and completely within a single clock cycle before any subsequent computation is needed. The convertFromDecimalCharacter operator prepares the binary64 result in advance, eliminating the need for multiple threads to overlap and hide latency, thus reducing processor complexity while maintaining performance.
4Ease of operation
If conventional processors read and write no more than 64 bits at a time, then register constraints are satisfied, but long decimal character sequences must be explicitly converted before use
Solution Approach 1:
The patent implements a universal convertFromDecimalCharacter operator that accepts up to 128 bytes of decimal character data and converts it to binary64 format in a single clock cycle. This multi-functional operator replaces the conventional limitation of reading only 64 bits at a time, enabling direct computation with long decimal sequences without explicit conversion overhead while maintaining compatibility with standard register widths.
Data Source
AI summary
A universal floating-point Instruction Set Architecture (ISA) compute engine implemented entirely in hardware. The ISA compute engine computes directly with human-readable decimal character sequence floating-point representation operands without first having to explicitly perform a conversion-to-binary-format process in software. A fully pipelined convertToBinaryFromDecimalCharacter hardware operator logic circuit converts one or more human-readable decimal character sequence floating-point representations to IEEE 754-2008 binary floating-point representations every clock cycle. Following computations by at least one hardware floating-point operator, a convertToDecimalCharacterFromBinary hardware conversion circuit converts the result back to a human-readable decimal character sequence floating-point representation.