Polyphase Decimation FIR Filters With Differential Coefficients
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Solution Overview
Problem
Existing polyphase decimation FIR filters face challenges in achieving low power consumption and small chip area due to high power dissipation from multiplication operations and overflow issues in integrator circuits.
Innovation Solution
The proposed solution involves a polyphase decimation FIR filter architecture that uses an integrator circuit with two's complement arithmetic and a polyphase FIR filter circuit with multiple independent multiplier accumulator circuits, employing differential coefficient methods to reduce coefficient precision and perform computations with modulo arithmetic, thereby minimizing power consumption and chip area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If traditional multiplication operations are used in FIR filters, then filtering accuracy is maintained, but power dissipation increases significantly
Solution Approach 1:
The patent changes the parameter of coefficient precision by using differential coefficient methods to represent filter coefficients with reduced bit precision. This parameter change allows maintaining filtering accuracy while significantly reducing the power dissipation from multiplication operations, as lower precision coefficients require less computational energy.
Solution Approach 2:
The patent substitutes traditional multiplication operations with a combination of addition and lookup table operations. By pre-computing and storing differential coefficient values in lookup tables, the power-intensive multiplication mechanism is replaced with simpler addition operations and memory access, reducing power dissipation while maintaining filtering performance.
2Measurement precision
If integrator word width is increased to prevent overflow, then computational accuracy is improved, but chip area increases
Solution Approach 1:
The patent applies modulo arithmetic to create periodic wrapping of integrator values. Instead of continuously increasing word width to prevent overflow, the system uses periodic modulo operations that wrap values within a fixed range, preventing overflow while maintaining a constant, smaller chip area for the integrator circuit.
Solution Approach 2:
The patent changes the parameter of arithmetic operation type by using modulo arithmetic instead of standard addition. This parameter change allows the integrator to operate with fixed, smaller word width while preventing overflow through periodic wrapping, thereby reducing chip area while maintaining computational accuracy within the modulo range.
3Loss of energy
If coefficient precision is reduced to lower power consumption, then power dissipation decreases, but filtering performance degrades
Solution Approach 1:
The patent introduces differential coefficients as an intermediary representation. Instead of using full-precision coefficients directly in multiplication, the system uses differential coefficients (differences between consecutive coefficients) which have lower precision requirements. This intermediary representation maintains filtering performance while enabling lower power consumption operations.
Solution Approach 2:
The patent segments the coefficient representation into differential components. By representing coefficients as differences between adjacent values, the system creates a segmented structure where each differential coefficient requires fewer bits. This segmentation allows reduced precision operations while maintaining the overall filtering characteristics through the cumulative effect of differential terms.
4Measurement precision
If standard FIR filter structure is used, then filtering accuracy is maintained, but device complexity and power consumption increase
Solution Approach 1:
The patent merges the multiplication and accumulation operations into a unified multiplier-accumulator structure that operates with reduced precision coefficients. By combining these operations and using differential coefficient representation, the system reduces device complexity while maintaining filtering accuracy, as the merged structure with lower precision requirements is simpler than traditional separate multiplication and addition stages.
Data Source
AI summary
A polyphase decimation FIR filter apparatus including a modulo integrator circuit configured to integrate input samples and to provide integrated input samples; and a polyphase FIR filter circuit configured to process the integrated input samples, the polyphase FIR filter circuit including a plurality of multiplier accumulator circuits, each configured to accumulate products of coefficients and respective integrated signal samples, wherein each of the multiplier accumulator circuits receives a subset of FIR filter coefficients, wherein the FIR filter coefficients are derived as the nth difference of original filter coefficients, where n is a number of integrators in the integrator circuit, and wherein the FIR filter circuit is configured to perform computation operations with modulo arithmetic.