High-Speed Decision Circuit With Precharge for Faster Clock Recovery
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Solution Overview
Problem
High-speed decision devices in clock and data recovery circuits face reduced speed due to the response time required for initial voltages on source sides of switch transistors, limiting their performance.
Innovation Solution
A high-speed decision device is designed with a differential amplifier circuit and an adjusting branch comprising MOS transistors to adjust the response speed of clock signal changes, allowing the circuit to start from an intermediate level when the clock signal transitions, thereby improving response time and resolution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a regenerative feedback circuit comprising switch transistors is used, then the decision device can restore signal levels, but the response time is reduced due to initial voltages on source sides of the switch transistors
Solution Approach 1:
The patent applies preliminary action by pre-charging the source nodes of the switch transistors to an intermediate voltage level (e.g., VDD/2) before the clock edge arrives. This is achieved through dedicated pre-charge paths that activate during the appropriate clock phase, ensuring that when the switch transistors turn on, no voltage buildup delay occurs at their source terminals, thus eliminating the response time penalty while maintaining regenerative feedback functionality
2Reliability
If the circuit waits for initial voltages to stabilize on source sides of switch transistors, then proper switching operation is ensured, but the overall speed of the decision device is reduced
Solution Approach 1:
The circuit performs preliminary voltage establishment by pre-charging the source nodes to the required intermediate level before the switching event. This pre-charge operation is timed to complete before the active clock edge, so when the switch transistors activate, the voltage conditions are already optimal for immediate switching action, eliminating the need to wait for voltage stabilization during the critical decision window
3Productivity
If the decision device operates at high speed, then data recovery performance is improved, but the circuit requires reduced response time which conflicts with the natural charging time of transistor source nodes
Solution Approach 1:
The patent implements preliminary action by establishing the voltage conditions at the source nodes of the switch transistors in advance, before the decision operation begins. This pre-charge mechanism ensures that when high-speed switching is required, the transistors can transition immediately without being limited by RC charging time constants, thus enabling high-speed operation while maintaining proper switching behavior
Solution Approach 2:
The circuit employs dynamic voltage control by using clock-phased pre-charge paths that activate and deactivate at specific times. The pre-charge operation is dynamically synchronized with the clock signal, allowing the source nodes to be charged to appropriate levels only when needed, and discharged or held at appropriate levels at other times, enabling the circuit to adapt its voltage conditions dynamically to match the timing requirements of high-speed operation
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances the response time and clock/data recovery performance of the high-speed decision device by allowing it to operate from an intermediate level during clock signal transitions, improving resolution and overall performance.
Implementation Method 1
a first MOS transistor (M1), wherein a gate of the first MOS transistor (M1) is connected to a first clock signal input end (CLK-), a source of the first MOS transistor (M1) is connected to the ground through a first resistor (R1), and a drain of the first MOS transistor (M1) is connected to the first adjusting point (Q1)
Data Source
Figure 1
Figure 2
AI summary
The invention relates to the technical field of high-speed data transmission, and more particularly, to a high-speed decision device which comprises a first branch and a second branch which are connected in parallel between a power supply end (VDD) and a ground end; wherein the first branch is used for providing a normal-phase input end (IN+), and the second branch is used for providing an inverted-phase input end (IN-); a first adjusting point (Q1) is arranged in the first branch, and a second adjusting point (Q2) is arranged in the second branch; and an adjusting branch (2) is arranged between the first adjusting point (Q1) and the second adjusting point (Q2), and the adjusting branch (2) is used for adjusting the response speed when the clock signal (CLK) changes. The technical scheme provided by the invention has the beneficial effects that the adjusting branch is added to adjust the response speed when the clock signal changes, so that the response time of the circuit is further improved, the resolution of the high-speed decision device is improved, and the clock and data recovery performance of the high-speed decision device is further improved.