Decision Feedback Comparator Circuit for ISI-Resistant Signal Latching
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Solution Overview
Problem
Current computer memory devices face challenges in improving performance due to Inter-Symbol Interference (ISI), which causes signal distortion and waveform broadening, affecting the accuracy of digital signal determination in comparator circuits.
Innovation Solution
The proposed solution involves a comparator circuit with a second-stage circuit and cross-coupled circuits that generate differential signals through mutual positive feedback, allowing for the selection of appropriate reference signals to eliminate ISI and improve operating speed by accelerating voltage changes during the sampling phase.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional comparator circuit is used, then the circuit structure is simple, but signal distortion occurs due to Inter-Symbol Interference (ISI) and the operating speed is limited
Solution Approach 1:
The comparator circuit is divided into multiple independent comparison stages (first comparison stage, second comparison stage, etc.), each handling different reference signal comparisons. This segmentation allows each stage to independently process signals with minimal ISI impact, improving overall signal determination accuracy while maintaining manageable circuit complexity through modular design
Solution Approach 2:
Differential signals are introduced as intermediary elements between the input signal and the final comparison output. The first and second differential signals serve as intermediate representations that capture signal characteristics at different reference levels, enabling more accurate signal determination by eliminating ISI through multi-stage differential comparison
2Measurement precision
If the sampling phase duration is extended to improve signal accuracy, then measurement precision improves, but the operating rate of the comparator decreases
Solution Approach 1:
The comparator operates in periodic cycles with distinct phases (sampling phase, regeneration phase, hold phase) controlled by clock signals. This periodic operation allows the circuit to complete rapid comparisons within fixed time intervals, maintaining high operating rates while ensuring sufficient sampling duration for accurate signal determination through the multi-stage comparison process
Solution Approach 2:
The circuit replaces extended temporal sampling with parallel spatial comparison using multiple comparison stages operating simultaneously. Instead of extending the sampling phase duration to improve accuracy, the invention uses multiple stages comparing against different reference signals in parallel, achieving high precision without sacrificing operating speed
3Speed
If cross-coupled circuits with mutual positive feedback are added to accelerate voltage changes, then the operating speed improves, but the circuit complexity increases
Solution Approach 1:
The cross-coupled circuits are merged with the comparison stages, where the feedback paths are integrated into the existing differential pair structures. This merging allows the positive feedback to accelerate voltage changes during the regeneration phase without requiring completely separate circuit blocks, thus improving speed while limiting the increase in overall circuit complexity through efficient integration
Data Source
AI summary
A comparator includes a second-stage circuit, a first input circuit, a second input circuit, a first cross-coupled circuit and a second cross-coupled circuit. The first input circuit is configured to generate a first data terminal voltage and a first reference terminal voltage. The first cross-coupled circuit is configured to perform mutual positive feedback on the first data terminal voltage and the first reference terminal voltage to generate a first differential signal. The second input circuit is configured to generate a second data terminal voltage and a second reference terminal voltage. The second cross-coupled circuit is configured to perform mutual positive feedback on the second data terminal voltage and the second reference terminal voltage to generate a second differential signal. The second-stage circuit is configured to amplify and latch the first differential signal or the second differential signal in a regeneration phase to output a comparison signal.