Decision Feedback Receiver Using Dual Trip Points for Lower BER

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Solution Overview

Problem

High-speed serial communication circuits in integrated circuits face challenges with power consumption and bit error rates due to the use of differential amplifiers, which are exacerbated by increasing data rates.

Innovation Solution

The implementation of two receiver circuits with adjustable input voltage trip points and a decision circuit that selects between them based on previous output data symbols, allowing for extended data valid windows and improved bit error rates without significant power increase.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If a differential amplifier is used to receive high-speed signals, then data transfer rate is improved, but power consumption increases

Engineering Contradiction:
Improvedata transfer rateVSAvoidpower consumption
Core Design Contradiction:
SpeedVSUse of energy by moving object

Solution Approach 1:

The receiver is divided into two separate receiver circuits, each optimized for different input voltage transition types (rising vs. falling edges). This segmentation allows each circuit to operate more efficiently for its specific transition type, reducing overall power consumption while maintaining high data transfer rates.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system dynamically selects between two different receiver circuits based on the input voltage transition type. The decision circuit determines which receiver circuit to use based on whether the input signal is transitioning from low-to-high or high-to-low, optimizing power efficiency adaptively.

Inventive Principle:
Principle #15Dynamics

2Productivity

If data transfer frequency is increased, then performance is improved, but bit error rate increases

Engineering Contradiction:
Improvedata transfer frequencyVSAvoidbit error rate
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

Each receiver circuit is specially optimized for a specific type of voltage transition (rising or falling edges). This local optimization ensures that each circuit operates at its peak performance for its designated transition type, maintaining low bit error rates even at high data transfer frequencies.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The system changes operational parameters by selecting different receiver circuits with different trip points based on the input transition type. This parameter adaptation allows the receiver to maintain optimal performance across different signal conditions, reducing bit errors at high speeds.

Inventive Principle:
Principle #35Parameter changes

3Use of energy by moving object

If voltage level is reduced for lower power operation, then power consumption is reduced, but signal reception reliability deteriorates

Engineering Contradiction:
Improvepower consumptionVSAvoidsignal reception reliability
Core Design Contradiction:
Use of energy by moving objectVSReliability

Solution Approach 1:

The receiver is segmented into two specialized circuits with different trip points, allowing each to operate efficiently at lower voltage levels for its specific transition type. This segmentation enables low-power operation while maintaining reliable signal reception through optimized circuit characteristics.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS10880042B1Serial data receiver with decision feedback equalization
Publication Date: 2020.12.29 APPLE INC
  • US10880042B1 patent drawing
  • US10880042B1 patent drawing
  • US10880042B1 patent drawing

AI summary

An apparatus includes first and second receiver circuits and a decision circuit. The first receiver circuit is configured to generate a first data symbol from a particular input data symbol of a plurality of input data symbols included in an input signal. The second receiver circuit is configured to generate a second data symbol from the particular input data symbol. The decision circuit is configured to select, using respective values of one or more previous output data symbols, either the first or second data symbol as a current output data symbol. In response to a change in value between successive input data symbols, the first and second receiver circuits are configured to generate the first and second data symbols with respective data valid windows with different durations.