Decision Feedback Equalizer With Multi-Speed Clocking
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Solution Overview
Problem
Conventional decision feedback equalizers (DFEs) in receiving channels are complex and susceptible to noise, which affects their performance in extracting data from transmission lines.
Innovation Solution
The proposed solution reduces the number of components in a DFE and outputs received data bits to a clock and data recovery circuit, improving the performance by using a three-stage DFE with summation blocks and flip-flops operating at different clock speeds to condition and separate even and odd data bits, and generate error weights for improved signal processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional DFE structure is used, then data extraction function is provided, but device complexity increases and noise susceptibility increases
Solution Approach 1:
The patent combines multiple DFE stages into a single integrated circuit structure where summation blocks and flip-flops operate at different clock speeds. The first and second summation blocks process data bits simultaneously, merging what would traditionally be separate processing stages into a unified architecture that reduces overall component count while maintaining equalization functionality.
Solution Approach 2:
The DFE is segmented into multiple functional blocks operating at different clock frequencies: a first summation block processing even data bits at a first clock speed, and a second summation block processing odd data bits at a second clock speed. This segmentation allows each block to operate optimally for its specific data processing task while reducing overall system complexity through parallel operation.
2Measurement precision
If conventional DFE structure is used, then equalization is provided, but bit error rate increases
Solution Approach 1:
The patent implements dynamic clocking where the first and second summation blocks operate at different clock speeds depending on the data processing requirements. The first summation block operates at a first clock speed for processing even data bits, while the second summation block operates at a second clock speed for processing odd data bits, allowing optimized performance for each processing stage and reducing bit errors.
Solution Approach 2:
The patent incorporates feedback mechanisms where error weights are generated and fed back to the summation blocks. The first and second summation blocks receive feedback signals that allow them to adjust their operation based on previous data processing results, continuously improving the bit error rate through adaptive equalization.
3Use of energy by moving object
If conventional DFE structure is used, then signal processing is provided, but power efficiency decreases
Solution Approach 1:
The patent uses periodic clocking with different frequencies for different processing stages. The first summation block is clocked at a first clock speed and the second summation block at a second clock speed, allowing the system to process data in periodic cycles optimized for each stage. This periodic action reduces power consumption by allowing clock signals to be turned off or reduced between cycles.
Data Source
AI summary
A circuit includes a summation circuit for receiving an input data signal and a feedback signal including a previous data bit. The summation circuit is configured to output a conditioned input data signal to a clock and data recovery circuit. A first flip-flop is coupled to an output of the summation circuit and is configured to receive a first set of bits of the conditioned input data signal and a first clock signal having a frequency that is less than a frequency at which the input data signal is received by the first summation circuit. A second flip-flop is coupled to the output of the summation circuit and is configured to receive a second set of bits of the conditioned input data signal and a second clock signal having a frequency that is less than the frequency at which the input data signal is received by the first summation circuit.