Decision Feedback Equalizer Parallel Processing Noise Reduction
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Solution Overview
Problem
As data rates increase in communication systems, signal loss and waveform degradation in transmission lines lead to challenges in accurately restoring data and clock signals, with existing decision feedback equalizers potentially amplifying noise due to feedback paths and requiring complex synchronization circuits.
Innovation Solution
A decision feedback equalizer is designed with multiple equalization calculation circuits, logic circuits, and selection circuits to perform parallel equalization calculations and data decision values, using threshold values to select appropriate logical values for data decision, thereby reducing noise amplification and improving signal processing efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If decision feedback equalizer uses feedback path to compensate signal degradation, then equalization performance is improved, but noise amplification occurs
Solution Approach 1:
The feedback path is segmented into multiple parallel calculation circuits, each handling different combinations of data decision values. This segmentation allows the system to process multiple hypotheses simultaneously and select the most accurate one, improving equalization performance while controlling noise amplification through diversified calculation paths.
Solution Approach 2:
The system performs preliminary equalization calculations for multiple possible data decision value combinations before the actual data decision is made. By pre-calculating multiple scenarios and selecting the best match, the system achieves accurate equalization without amplifying noise from sequential feedback iterations.
2Productivity
If decision feedback equalizer uses traditional sequential processing, then circuit complexity is reduced, but processing speed decreases
Solution Approach 1:
The system transitions from sequential time-domain processing to parallel space-domain processing by introducing multiple calculation circuits that operate simultaneously. This dimensional change from sequential to parallel architecture enables high-speed processing while managing circuit complexity through structured organization of the parallel paths.
Solution Approach 2:
The invention creates multiple copies of the equalization calculation circuit, each configured to handle different data decision value combinations. These copied circuits operate in parallel, achieving high processing speed while the modular copying approach keeps circuit complexity manageable through repetition of standardized units.
3Productivity
If decision feedback equalizer processes data at high data rates, then communication capacity is improved, but signal loss and waveform degradation increase
Solution Approach 1:
The high data rate signal is segmented into multiple parallel processing paths, each handling specific combinations of data decision values. This segmentation allows the system to process high-rate data while maintaining signal quality through simultaneous multi-hypothesis evaluation and selection of the most accurate reconstruction.
Solution Approach 2:
The system performs preliminary signal reconstruction and evaluation for multiple possible data sequences before final decision. This preliminary action enables accurate signal recovery at high data rates by pre-computing multiple scenarios and selecting the best match, thereby maintaining reliability despite increased data rate challenges.
Data Source
AI summary
A decision feedback equalizer includes: L equalization calculation circuits to perform an equalization calculation of a first sample of input data for each of M combinations of data decision values of a second sample sampled from the input data before sampling the first sample; a first logic circuit to generate first M logical values by selecting and arranging calculation values of M calculation values calculated by at least one equalization calculation circuit among the L equalization calculation circuits based on a data decision value for a third sample sampled before sampling the first data; and a selection circuit to select one of the first M logical values based on a data decision value for a fourth sample sampled before sampling the third sample, and to output the selected logical value as a data decision value of the first sample.