Decision Feedback Equalizer With In-Latch Feedback Summing
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Solution Overview
Problem
Conventional decision feedback equalizers face challenges in compensating intersymbol interference for high-speed signals, as the feedback loop delay is not sufficiently reduced, limiting the operational data rate of the receiver.
Innovation Solution
The proposed decision feedback equalizer design includes an amplifier with a sampling block, a latch circuit, and a buffer, where the operation for adding the output from the latch block and the feedback signal occurs during the latch operation, effectively reducing the feedback loop delay to TLA+TBUF, thereby enhancing the compensation of intersymbol interference for high-speed signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the feedback loop delay is reduced to increase operational data rate, then the productivity increases, but the device complexity increases due to additional components like buffer and modified amplifier structure
Solution Approach 1:
The adder function is merged into the amplifier structure, specifically integrating the feedback signal addition with the existing latch block operation. This consolidation eliminates separate adder components and reduces overall device complexity while achieving the goal of reducing feedback loop delay to increase operational data rate
Solution Approach 2:
The amplifier is designed to perform multiple functions: signal amplification, feedback signal addition, and latch operation. By making the amplifier multi-functional, the patent reduces the need for separate dedicated components, thereby managing device complexity while improving productivity through reduced feedback loop delay
2Loss of time
If the feedback loop delay is reduced by optimizing component operations, then the loss of time decreases, but the manufacturing precision requirements increase
Solution Approach 1:
The adder operation is performed concurrently with the latch block operation rather than sequentially. By performing the addition action in advance of what would traditionally be a separate step, the patent reduces feedback loop delay while managing timing synchronization requirements through parallel execution of operations
3Device complexity
If conventional DFE structure is used, then the device complexity is lower, but the intersymbol interference compensation is insufficient for high-speed signals
Solution Approach 1:
The adder function is merged into the amplifier structure, allowing the feedback signal to be added during the latch operation. This integration improves ISI compensation effectiveness for high-speed signals by reducing feedback loop delay, while the merging itself helps manage device complexity through component consolidation
Solution Approach 2:
The patent implements a feedback mechanism where the amplifier output is fed back through a buffer and added to the input signal via the integrated adder. This feedback loop enables continuous ISI compensation, improving reliability for high-speed signal transmission while the integrated structure keeps device complexity manageable
Data Source
AI summary
An amplifier output from an amplifier to an SR latch is used as a feedback signal through a buffer. An adder having a combination of an addition unit and an xh block is provided within the amplifier and transmits a feedback signal (analog signal) generated from the feedback signal FBD (digital signal) by the xh block to the addition unit and adds it to an output from a latch block. In the amplifier, the operation for adding the output from the latch block and the feedback signal occurs during a latch operation in the latch block.