Decision Lookahead Digital Feedback Equalizer Tree
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Solution Overview
Problem
Implementing a digital feedback equalizer (DFE) at high data rates is challenging due to the need to make and propagate a decision every unit interval, leading to high latency and partial DFE implementations that degrade bit error rate (BER) and clock data recovery (CDR) performance.
Innovation Solution
The implementation of a full 1-tap DFE with reduced latency and fewer physical flops is achieved through the use of multiple symbol lookahead processing and loop unrolling, allowing for faster computation and propagation of decisions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a digital feedback equalizer (DFE) is implemented at high data rates, then bit error rate (BER) performance is improved, but latency increases due to the necessity of making and propagating decisions every unit interval
Solution Approach 1:
The patent implements lookahead processing where decisions for multiple future symbols are made in advance based on current and past symbols. This preliminary action allows the DFE to propagate decisions more efficiently without waiting for each unit interval, thereby reducing latency while maintaining BER performance improvement
Solution Approach 2:
The patent segments the DFE operation into multiple parallel decision paths using loop unrolling techniques. By dividing the single sequential decision-making process into parallel segments that can operate simultaneously, the system reduces the time required for decision propagation while maintaining the full DFE functionality for BER improvement
2Reliability
If a full 1-tap DFE is implemented, then BER performance is improved, but device complexity increases due to the number of physical flops required
Solution Approach 1:
The patent merges multiple decision-making operations into a single parallel structure using loop unrolling. Instead of implementing separate physical flops for each decision step, the patent combines them into a unified parallel architecture that achieves the same DFE functionality with fewer physical components while maintaining BER performance
Solution Approach 2:
By performing decisions in advance through lookahead processing, the patent reduces the number of sequential operations required. This preliminary action allows the system to achieve full DFE functionality with fewer physical flops, as decisions are made in parallel rather than requiring separate sequential hardware stages
Data Source
AI summary
A digital feedback equalizer (DFE) includes a plurality of loop unrolling circuits and a first plurality of multiplexers. Each loop unrolling circuit of the plurality of loop unrolling circuits is configured to receive an input symbol, generate a plurality of modified symbols based on the input symbol and a plurality of symbol versions associated with a previously generated output symbol, and generate a plurality of output symbols based on the plurality of modified symbols. The first plurality of multiplexers is coupled to a first loop unrolling circuit of the plurality of loop unrolling circuits. The first plurality of multiplexers is configured to output one or more of the plurality of output symbols generated by the first loop unrolling circuit based on a selection signal including one or more of the plurality of output symbols generated by a second loop unrolling circuit of the plurality of loop unrolling circuits.