Decision Tree Leaf-Node Parallelism for Low-Latency Inference
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Solution Overview
Problem
Decision tree inference processing in machine learning is inherently sequential, leading to pipeline slowdowns due to memory access delays, which can be exacerbated in production environments.
Innovation Solution
A decision tree inference accelerator processes decision nodes in parallel, using predetermined path vectors and masks to determine leaf node selection independently for each leaf node, allowing full parallel processing of decision nodes and leaf nodes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If decision tree inference processing is performed sequentially as prescribed by the decision tree structure, then the processing logic is simple and easy to implement, but the processing speed is slow due to pipeline slowdowns from skip sequential memory accesses
Solution Approach 1:
The patent segments the decision tree processing into independent path evaluations for each leaf node. Each leaf node's path from root to leaf is evaluated independently using bitwise operations, allowing parallel processing of multiple paths simultaneously. This segmentation transforms the inherently sequential decision tree traversal into parallelizable operations while maintaining the logical structure of the decision tree.
Solution Approach 2:
The patent replaces the mechanical sequential traversal mechanism with bitwise logical operations (AND, OR, XOR, NOT). Instead of physically following one path at a time through the decision tree, the system uses bitwise operations to evaluate all paths in parallel, substituting the mechanical sequential access pattern with computational logical operations that can be executed simultaneously.
2Productivity
If decision tree inference is offloaded to a peripheral computational device, then CPU resource consumption is reduced, but the complexity of the processing system increases
Solution Approach 1:
The patent introduces a specialized decision tree inference accelerator as an intermediary device between the CPU and memory. This peripheral computational device is specifically designed to handle decision tree inference operations, offloading the computational burden from the CPU while maintaining a clear interface for data input and result output. The intermediary device resolves the contradiction by providing dedicated hardware acceleration without requiring complete system redesign.
3Loss of time
If parallel processing is implemented at the leaf node level using predetermined path vectors, then processing throughput is enhanced and latency is reduced, but the memory access pattern becomes more complex
Solution Approach 1:
The patent performs preliminary action by pre-computing and storing the path vectors for each leaf node in the decision tree. These path vectors, which represent the sequence of decisions required to reach each leaf, are calculated in advance and stored in memory. During inference, the pre-computed path vectors are retrieved and used directly for parallel evaluation, eliminating the need for dynamic path computation and reducing processing latency.
Data Source
AI summary
Processing within a computing environment is facilitated by obtaining, by a decision tree inference accelerator, a decision node result vector based on processing an input data vector through decision nodes of a decision tree. Further, the processing is facilitated by accelerating, by the decision tree inference accelerator, leaf node processing of the decision node result vector. The decision tree inference accelerator facilitates, based on predetermined path vectors through the decision tree to each leaf node of the plurality of leaf nodes, processing of the decision node result vector by the plurality of leaf nodes in parallel, and determining therefrom which leaf node of the plurality of leaf nodes is selected.