Decision Tree Learning Device Buffering Strategy

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Solution Overview

Problem

Current machine learning methods, particularly gradient boosting decision trees (GBDT), face challenges in processing large amounts of data due to high calculation loads and long processing times, especially when dealing with large datasets like images and voice data, limiting their accuracy and speed in real-world applications.

Innovation Solution

A learning device configured with a data storage unit, learning unit, first buffer unit, and second buffer unit, which determines whether to branch learning data to one node or another based on branch conditions, and buffers data up to a predetermined capacity before writing it into continuous addresses, optimizing data storage and retrieval for faster processing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If gradient boosting is used to perform learning at higher speed, then processing speed is improved, but calculation load increases and processing time becomes problematic when performing multiple learning adjustments and model ensembles

Engineering Contradiction:
Improvelearning processing speedVSAvoidtotal processing time
Core Design Contradiction:
SpeedVSLoss of time

Solution Approach 1:

The patent segments the learning data into multiple blocks and uses buffer memory to cache data for specific nodes. This allows the system to process data in manageable chunks rather than handling the entire dataset at once, reducing the calculation load for each iteration while maintaining high processing speed. The segmentation enables efficient data distribution across multiple processing units.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent performs preliminary actions by pre-calculating and caching data in buffer memory before the actual learning processing begins. This preliminary data preparation and caching reduces the calculation load during subsequent learning iterations, allowing the system to achieve both high speed and reduced total processing time when performing multiple learning adjustments and model ensembles.

Inventive Principle:
Principle #10Preliminary action

2Measurement precision

If pieces of processing of causing sample data to branch are performed in order based on branch condition, then optimal branch condition is calculated for each node, but processing time becomes long and large amount of sample data cannot be handled

Engineering Contradiction:
Improvebranch condition optimizationVSAvoidprocessing time
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The patent segments the sequential processing into parallel operations by using buffer memory to store data for multiple nodes simultaneously. This allows the system to calculate optimal branch conditions for multiple nodes in parallel rather than sequentially, maintaining measurement precision while significantly reducing processing time and enabling handling of large amounts of sample data.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces buffer memory as an additional dimension for data storage and processing. By moving data to buffer memory, the system can access and process data for multiple nodes simultaneously in parallel, transforming the sequential one-dimensional processing into a multi-dimensional approach that reduces processing time while maintaining optimization accuracy.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Ease of operation

If SRAM is used as storage medium for sample data, then random access is enabled, but only small amount of data within chip can be handled and large amount of sample data cannot be learned

Engineering Contradiction:
Improverandom access capabilityVSAvoidamount of handleable data
Core Design Contradiction:
Ease of operationVSQuantity of substance

Solution Approach 1:

The patent implements a nested memory structure where buffer memory is embedded within the processing system and contains both SRAM for random access and external memory for large data storage. This nested architecture allows the system to maintain the ease of random access provided by SRAM while extending the quantity of handleable data by utilizing the larger capacity of external memory stored in the buffer.

Inventive Principle:
Principle #7Nested doll (Nesting)

Solution Approach 2:

The buffer memory acts as an intermediary between the SRAM and external memory. It provides random access capability for small datasets while simultaneously serving as a gateway to external memory for handling large amounts of sample data. This intermediary structure resolves the contradiction by mediating between the need for fast random access and the need to handle large data quantities.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS11475314B2Learning device and learning method
Publication Date: 2022.10.18 RICOH CO LTD
  • US11475314B2 patent drawing
  • US11475314B2 patent drawing
  • US11475314B2 patent drawing

AI summary

A learning device includes a data storage unit configured to store learning data for learning a decision tree; a learning unit configured to determine whether to cause learning data stored in the data storage unit to branch to one node or to the other node of lower nodes of a node based on a branch condition for the node of the decision tree; and a first buffer unit and a second buffer unit configured to buffer learning data determined to branch to the one node and the other node, respectively, by the learning unit up to capacity determined in advance. The first buffer unit and the second buffer unit are configured to, in response to buffering learning data up to the capacity determined in advance, write the learning data into continuous addresses of the data storage unit for each predetermined block.